Patents by Inventor Yudan DENG

Yudan DENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip and chip test method
    Patent number: 12019117
    Abstract: A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 25, 2024
    Assignee: Shanghai Biren Technology Co., Ltd
    Inventors: Kai Lei, Yikai Liang, Yudan Deng, Linglan Zhang, Jinfu Ye, Huan Liu
  • Chip and chip testing method
    Patent number: 11835595
    Abstract: A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: December 5, 2023
    Assignee: Shanghai Biren Technology Co., Ltd
    Inventors: Kai Lei, Yikai Liang, Yudan Deng, Linglan Zhang, Jinfu Ye, Huan Liu
  • CHIP AND CHIP TESTING METHOD
    Publication number: 20230176141
    Abstract: A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.
    Type: Application
    Filed: August 11, 2022
    Publication date: June 8, 2023
    Applicant: Shanghai Biren Technology Co.,Ltd
    Inventors: Kai LEI, Yikai LIANG, Yudan DENG, Linglan ZHANG, Jinfu YE, Huan LIU
  • CHIP AND CHIP TEST METHOD
    Publication number: 20230176118
    Abstract: A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.
    Type: Application
    Filed: August 16, 2022
    Publication date: June 8, 2023
    Applicant: Shanghai Biren Technology Co.,Ltd
    Inventors: Kai LEI, Yikai LIANG, Yudan DENG, Linglan ZHANG, Jinfu YE, Huan LIU