Patents by Inventor Yudhishthir Prasad Kandel

Yudhishthir Prasad Kandel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11900042
    Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: February 13, 2024
    Assignee: Synopsys, Inc.
    Inventors: Kevin Dean Lucas, Yudhishthir Prasad Kandel, Ulrich Welling, Ulrich Karl Klostermann, Zachary Adam Levinson
  • Patent number: 11468222
    Abstract: A method, includes, in part, defining a continuous signal, defining a threshold value, calibrating the continuous signal and the threshold value from measurements made on edges of one or more patterns on a mask and corresponding edges of the patterns on a wafer, convolving the continuous signal with a kernel to form a corrected signal, and establishing, by a processor, a probability of forming an edge at a point along the corrected signal in accordance with a difference between the value of the corrected signal at the point and the calibrated threshold value. The kernel is calibrated using the same measurements made on the patterns' edges.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 11, 2022
    Assignee: Synopsys, Inc.
    Inventors: Yudhishthir Prasad Kandel, Lawrence S. Melvin, III
  • Patent number: 11415897
    Abstract: Calibrating stochastic signals in compact modeling is provided by obtaining data of process variations in producing a resist mask; calibrating a continuous compact model of the resist mask based on the data; evaluating the continuous compact model against a stochastic compact model that is based on the data; choosing a functional description of an edge location distribution for the stochastic compact model; mapping image parameters from the evaluation to edge distribution parameters according to the functional description; determining an edge location range for the stochastic compact model based on scaled measurements from the image parameters; calibrating a threshold for the resist mask and updating parameters of the stochastic compact model to reduce a difference between the data and a modeled Line Edge Roughness (LER) value; and outputting the stochastic compact model.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 16, 2022
    Assignee: Synopsys, Inc.
    Inventors: Zachary Adam Levinson, Yudhishthir Prasad Kandel, Ulrich Welling
  • Patent number: 11402742
    Abstract: An EUV mask absorber formed on a semiconductor structure, includes, in part a sidewall forming am angle relative to a surface of the semiconductor structure that is less than 90 degrees. The sidewall includes a layer of reflective material. The semiconductor structure may include, in part, a multitude of layers. The semiconductor structure may be disposed on a glass substrate, a silicon substrate, or the like. The EUV mask absorber is adapted to shift a phase of the EUV light passing therethrough. The EUV mask absorber may further include, in part, a layer of Ruthenium near a bottom surface of the absorber structure. The EUV mask absorber may further includes, in part, a layer of reflective material near a top surface of the absorber structure. The EUV mask absorber may further include, in part, Tantalum Oxynitride.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: August 2, 2022
    Assignee: Synopsys, Inc.
    Inventors: Lawrence S. Melvin, III, Yudhishthir Prasad Kandel
  • Publication number: 20220146945
    Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 12, 2022
    Inventors: Kevin Dean Lucas, Yudhishthir Prasad Kandel, Ulrich Welling, Ulrich Karl Klostermann, Zachary Adam Levinson
  • Patent number: 11314171
    Abstract: Certain aspects relate to a method for improving a lithography configuration. In the lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focus exposure window (FEW). The defect-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of defects on the wafer. The defect-based FEW is determined based on a predicted probability distribution for occurrence of defects on the wafer. A processor also determines a critical dimension (CD)-based FEW. The CD-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of CD variation on the wafer. It is determined based on predicted CDs on the wafer. The lithography configuration is modified based on increasing an area of overlap between the defect-based FEW and the CD-based FEW.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: April 26, 2022
    Assignee: Synopsys, Inc.
    Inventors: Lawrence S. Melvin, III, Yudhishthir Prasad Kandel, Qiliang Yan, Ulrich Karl Klostermann
  • Publication number: 20210382394
    Abstract: Calibrating stochastic signals in compact modeling is provided by obtaining data of process variations in producing a resist mask; calibrating a continuous compact model of the resist mask based on the data; evaluating the continuous compact model against a stochastic compact model that is based on the data; choosing a functional description of an edge location distribution for the stochastic compact model; mapping image parameters from the evaluation to edge distribution parameters according to the functional description; determining an edge location range for the stochastic compact model based on scaled measurements from the image parameters; calibrating a threshold for the resist mask and updating parameters of the stochastic compact model to reduce a difference between the data and a modeled Line Edge Roughness (LER) value; and outputting the stochastic compact model.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 9, 2021
    Inventors: Zachary Adam LEVINSON, Yudhishthir Prasad KANDEL, Ulrich WELLING
  • Publication number: 20210088913
    Abstract: Certain aspects relate to a method for improving a lithography configuration. In the lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focus exposure window (FEW). The defect-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of defects on the wafer. The defect-based FEW is determined based on a predicted probability distribution for occurrence of defects on the wafer. A processor also determines a critical dimension (CD)-based FEW. The CD-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of CD variation on the wafer. It is determined based on predicted CDs on the wafer. The lithography configuration is modified based on increasing an area of overlap between the defect-based FEW and the CD-based FEW.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 25, 2021
    Inventors: Lawrence S. Melvin, III, Yudhishthir Prasad Kandel, Qiliang Yan, Ulrich Karl Klostermann