Abstract: A silicon carbide MOSFET device is disclosed. The silicon carbide MOSFET device includes a gate oxide layer which is constituted by a first gate oxide layer and a second gate oxide layer. A thickness of the second gate oxide layer is larger than a thickness of the first gate oxide layer. Through dividing the gate oxide layer into two parts with different thicknesses, i.e., enabling the gate oxide layer to have a staircase shape, an electric field strength of the gate oxide layer can be effectively reduced, while a threshold voltage and a gate control property of the device are not affected. An on-resistance of the device can be reduced through increasing a width of a JFET region. A method for manufacturing the silicon carbide MOSFET device is further disclosed.

Abstract: A silicon carbide MOSFET device is disclosed. The silicon carbide MOSFET device includes a gate oxide layer which is constituted by a first gate oxide layer and a second gate oxide layer. A thickness of the second gate oxide layer is larger than a thickness of the first gate oxide layer. Through dividing the gate oxide layer into two parts with different thicknesses, i.e., enabling the gate oxide layer to have a staircase shape, an electric field strength of the gate oxide layer can be effectively reduced, while a threshold voltage and a gate control property of the device are not affected. An on-resistance of the device can be reduced through increasing a width of a JFET region. A method for manufacturing the silicon carbide MOSFET device is further disclosed.

Abstract: An IGBT device and a method for packaging a whole-wafer IGBT chip. The IGBT device comprises: an entire wafer IGBT chip, the upper surface thereof comprising a central gate connection zone and a plurality of emitter connection zones surrounding the central gate connection zone, and the lower surface thereof comprising a collecting zone, wherein the emitter connection zones located on the surface of a failure cellular zone of the chip are thinned; a collector washer which is fixed on the lower surface of the chip, and an emitter washer which is fixed on the upper surface of the chip; a collector electrode which is electrically contacted with the collector washer, and an emitter electrode which is electrically contacted with the emitter washer; and a gate leading wire which is connected to the central gate connection zone.

Abstract: An IGBT device and a method for packaging a whole-wafer IGBT chip. The IGBT device comprises: an entire wafer IGBT chip, the upper surface thereof comprising a central gate connection zone and a plurality of emitter connection zones surrounding the central gate connection zone, and the lower surface thereof comprising a collecting zone, wherein the emitter connection zones located on the surface of a failure cellular zone of the chip are thinned; a collector washer which is fixed on the lower surface of the chip, and an emitter washer which is fixed on the upper surface of the chip; a collector electrode which is electrically contacted with the collector washer, and an emitter electrode which is electrically contacted with the emitter washer; and a gate leading wire which is connected to the central gate connection zone.