Patents by Inventor Yue CHAO
Yue CHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106442Abstract: Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Jianjun YU, Yue CHAO, Tomas O'SULLIVAN, Lai Kan LEUNG
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Publication number: 20220413455Abstract: The present invention discloses an adaptive-learning intelligent scheduling unified computing frame and system for industrial personalized customized production.Type: ApplicationFiled: November 13, 2020Publication date: December 29, 2022Inventors: ZAIXING HE, YUE CHAO, DONGSHENG YANG, ZHILE YANG
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Patent number: 11387833Abstract: A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.Type: GrantFiled: September 3, 2021Date of Patent: July 12, 2022Assignee: QUALCOMM IncorporatedInventors: Alvin Siu-Chi Li, Yue Chao, Dongmin Park, Heui In Yoon, Tomas O'Sullivan, Jianjun Yu, Yiwu Tang
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Patent number: 11342927Abstract: Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.Type: GrantFiled: June 28, 2021Date of Patent: May 24, 2022Assignee: QUALCOMM IncorporatedInventors: Younghyun Lim, Yiwu Tang, Dongmin Park, Yunliang Zhu, Mustafa Keskin, Yue Chao
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Patent number: 11290058Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.Type: GrantFiled: October 22, 2020Date of Patent: March 29, 2022Assignee: QUALCOMM IncorporatedInventors: Yue Chao, Yinghan Wang, Marco Zanuso, Rajagopalan Rangarajan
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Patent number: 11264995Abstract: A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signaType: GrantFiled: October 26, 2020Date of Patent: March 1, 2022Assignee: QUALCOMM IncorporatedInventors: Yue Chao, Yiwu Tang, Yunliang Zhu, Dongmin Park, Jingcheng Zhuang
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Patent number: 11025260Abstract: An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and multiple error determiners. The loop filter includes a filter input node and a filter output node. The VCO includes a VCO input node and a VCO output node. The VCO input node is coupled to the filter output node. The frequency divider includes a divider input node and multiple divider output nodes. The divider input node is coupled to the VCO output node. The multiple error determiners are coupled between the multiple divider output nodes and the filter input node.Type: GrantFiled: August 26, 2020Date of Patent: June 1, 2021Assignee: QUALCOMM IncorporatedInventors: Yue Chao, Marco Zanuso, Rajagopalan Rangarajan, Yiwu Tang
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Patent number: 10990117Abstract: Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.Type: GrantFiled: September 5, 2019Date of Patent: April 27, 2021Assignee: QUALCOMM IncorporatedInventors: Yue Chao, Marco Zanuso, Rajagopalan Rangarajan, Yiwu Tang
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Publication number: 20210072778Abstract: Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.Type: ApplicationFiled: September 5, 2019Publication date: March 11, 2021Inventors: Yue CHAO, Marco ZANUSO, Rajagopalan RANGARAJAN, Yiwu TANG
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Publication number: 20210044253Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Inventors: Yue CHAO, Yinghan WANG, Marco ZANUSO, Rajagopalan RANGARAJAN
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Patent number: 10848100Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.Type: GrantFiled: September 17, 2018Date of Patent: November 24, 2020Assignee: QUALCOMM IncorporatedInventors: Yue Chao, Yinghan Wang, Marco Zanuso, Rajagopalan Rangarajan
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Publication number: 20200091866Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.Type: ApplicationFiled: September 17, 2018Publication date: March 19, 2020Inventors: Yue CHAO, Yinghan WANG, Marco ZANUSO, Rajagopalan RANGARAJAN
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Patent number: 10535949Abstract: An electrical receptacle connector includes an insulative housing forming a pair of receiving slots, two pairs of contacts are retained in the housing and located by two sides of the corresponding receiving slots, respectively. Each contact has a frame having four sides with a pair of first spring arms extending from two opposite sides toward each other and extending into the receiving slot with the corresponding contact points at different levels. A second spring arm extends from another side into the receiving slot. A deflection direction of the first spring arms is perpendicular to that of the second spring arm, and the first spring arms contact one side of the blade type contact of the plug connector and the second spring arm contacts another side of the blade type contact of the plug connector.Type: GrantFiled: November 15, 2018Date of Patent: January 14, 2020Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventors: Jun Lin, Yue-Chao Zhao, Kuo-Chun Hsu
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Publication number: 20190148872Abstract: An electrical receptacle connector includes an insulative housing forming a pair of receiving slots, two pairs of contacts are retained in the housing and located by two sides of the corresponding receiving slots, respectively. Each contact has a frame having four sides with a pair of first spring arms extending from two opposite sides toward each other and extending into the receiving slot with the corresponding contact points at different levels. A second spring arm extends from another side into the receiving slot. A deflection direction of the first spring arms is perpendicular to that of the second spring arm, and the first spring arms contact one side of the blade type contact of the plug connector and the second spring arm contacts another side of the blade type contact of the plug connector.Type: ApplicationFiled: November 15, 2018Publication date: May 16, 2019Inventors: JUN LIN, YUE-CHAO ZHAO, KUO-CHUN HSU
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Patent number: 9991631Abstract: An electrical connector (100) includes: an insulative housing having a base (11) and a pair of side walls (12), each side wall having a resilient inner arm (121) and a stationary outer arm (122); and plural contacts (2) retained to the insulative housing, wherein the resilient inner arm extends along a horizontal, front-to-back direction and has a front end operable in both a vertical, top-to-bottom direction and the horizontal, front-to-back direction to move toward the stationary outer arm.Type: GrantFiled: August 4, 2017Date of Patent: June 5, 2018Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventors: Yue-Chao Zhao, Zhi-Jian Chen, Lai-Ang Hu
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Publication number: 20180040977Abstract: An electrical connector (100) includes: an insulative housing having a base (11) and a pair of side walls (12), each side wall having a resilient inner arm (121) and a stationary outer arm (122); and plural contacts (2) retained to the insulative housing, wherein the resilient inner arm extends along a horizontal, front-to-back direction and has a front end operable in both a vertical, top-to-bottom direction and the horizontal, front-to-back direction to move toward the stationary outer arm.Type: ApplicationFiled: August 4, 2017Publication date: February 8, 2018Inventors: Yue-Chao ZHAO, Zhi-Jian CHEN, Lai-Ang HU