Patents by Inventor Yue-Der Chih
Yue-Der Chih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935620Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.Type: GrantFiled: June 21, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
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Publication number: 20210312960Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der CHIH, Cheng-Hsiung KUO, Gu-Huan LI, Chien-Yin LIU
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Patent number: 11043249Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes a location-related memory cell and a refresh module. The location-related memory cell is coupled to a bit line. The refresh module is configured to refresh the location-related memory cell by reading data stored in the location-related memory cell and then writing the data back to the location-related memory cell in a condition that a target memory cell that is coupled to the bit line is programmed or erased. A method for memory cell programming and erasing with refreshing operation is also disclosed herein.Type: GrantFiled: November 6, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
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Publication number: 20200075068Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes a location-related memory cell and a refresh module. The location-related memory cell is coupled to a bit line. The refresh module is configured to refresh the location-related memory cell by reading data stored in the location-related memory cell and then writing the data back to the location-related memory cell in a condition that a target memory cell that is coupled to the bit line is programmed or erased. A method for memory cell programming and erasing with refreshing operation is also disclosed herein.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der CHIH, Cheng-Hsiung KUO, Gu-Huan LI, Chien-Yin LIU
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Patent number: 10475490Abstract: A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.Type: GrantFiled: October 9, 2017Date of Patent: November 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
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Patent number: 10281942Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: GrantFiled: February 26, 2018Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Patent number: 10277118Abstract: In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of a first capacitive element. The second node is coupled with a first end of a second capacitive element. A first end of a first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element and a first end of a second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage.Type: GrantFiled: September 29, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Qing Dong, Tien-Chun Yang, Yue-Der Chih
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Patent number: 10180877Abstract: The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.Type: GrantFiled: May 12, 2016Date of Patent: January 15, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yin Liu, Hsueh-Chih Yang, Kuan-Chun Chen, Yue-Der Chih, Yi-Chun Shih
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Patent number: 10141063Abstract: A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell.Type: GrantFiled: November 8, 2013Date of Patent: November 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li
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Publication number: 20180188756Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: ApplicationFiled: February 26, 2018Publication date: July 5, 2018Inventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Patent number: 10008253Abstract: A memory cell includes a plurality of thyristors each having a first end and a second. The memory cell further includes a plurality of bit-lines. Each of the plurality of thyristors are electrically coupled to one of the plurality of bit-lines at a first end. A local word line is electrically coupled to the second end of each of the thyristors. A selector is electrically coupled to the local word line. The selector is configured to selectively electrically couple the local word line to a data line.Type: GrantFiled: August 1, 2016Date of Patent: June 26, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yue-Der Chih, Carlos H. Diaz, Jean-Pierre Colinge, Jonathan Tsung-Yung Chang
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Patent number: 9934864Abstract: A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.Type: GrantFiled: February 2, 2017Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Patent number: 9915966Abstract: A device includes a proportional-to-absolute-temperature (PTAT) current source having a bandgap reference voltage node, and a negative temperature dynamic load having an input terminal electrically connected to the bandgap reference voltage node.Type: GrantFiled: August 22, 2013Date of Patent: March 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Cheng Chou, Yue-Der Chih
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Patent number: 9910451Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: GrantFiled: February 17, 2014Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Patent number: 9899079Abstract: A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.Type: GrantFiled: February 8, 2016Date of Patent: February 20, 2018Assignee: TAIWAN SEMINCONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yang Chang, Chia-Fu Lee, Wen-Ting Chu, Yue-Der Chih
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Publication number: 20180033471Abstract: A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.Type: ApplicationFiled: October 9, 2017Publication date: February 1, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der CHIH, Cheng-Hsiung KUO, Gu-Huan LI, Chien-Yin LIU
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Publication number: 20180026530Abstract: In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of a first capacitive element. The second node is coupled with a first end of a second capacitive element. A first end of a first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element and a first end of a second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage.Type: ApplicationFiled: September 29, 2017Publication date: January 25, 2018Inventors: Qing DONG, Tien-Chun YANG, Yue-Der CHIH
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Publication number: 20170329669Abstract: The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to detect a location one to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.Type: ApplicationFiled: May 12, 2016Publication date: November 16, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yin LIU, Hsueh-Chih YANG, Kuan-Chun CHEN, Yue-Der CHIH, Yi-Chun SHIH
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Patent number: 9812182Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.Type: GrantFiled: August 29, 2016Date of Patent: November 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
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Patent number: 9806064Abstract: A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.Type: GrantFiled: March 16, 2016Date of Patent: October 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chang Yu, Kai-Chun Lin, Yue-Der Chih