Patents by Inventor Yue-Han Wu

Yue-Han Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111588
    Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Jing Jing Wei, Yue Wang, Shu Jun Tang, Yang Kang, Yi Fan Wu, Qi Han Zheng, Jia Lin Wang
  • Patent number: 10965131
    Abstract: A charging protection device comprises a universal serial bus (USB) interface, a resistance circuit, a detection circuit and a control circuit. The universal serial bus interface includes a configuration channel. The resistance circuit includes a pull-down resistor coupled between the configuration channel and a ground GND. The detection circuit is configured to detect an abnormal charging condition. The detection circuit generates an abnormal signal when the abnormal charging condition occurs. The control circuit is coupled to the detection circuit and configured to change a voltage value on the pull-down resistor to be out of a preset voltage range according to the abnormal signal.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 30, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Wei-Gen Chung, Chien-Chung Lo, Ming-Ting Tsai, Yue-Han Wu, Tsung-Han Wu
  • Publication number: 20180205243
    Abstract: A charging protection device comprises a universal serial bus (USB) interface, a resistance circuit, a detection circuit and a control circuit. The universal serial bus interface includes a configuration channel. The resistance circuit includes a pull-down resistor coupled between the configuration channel and a ground GND. The detection circuit is configured to detect an abnormal charging condition. The detection circuit generates an abnormal signal when the abnormal charging condition occurs. The control circuit is coupled to the detection circuit and configured to change a voltage value on the pull-down resistor to be out of a preset voltage range according to the abnormal signal.
    Type: Application
    Filed: December 22, 2017
    Publication date: July 19, 2018
    Inventors: Wei-Gen Chung, CHIEN-CHUNG LO, Ming-Ting Tsai, Yue-Han Wu, TSUNG-HAN WU
  • Patent number: 9653998
    Abstract: A boost converter and a power control method thereof. The boost converter includes an inductor, a first switch unit, a second switch unit, a discharging loop and a detecting circuit. The inductor is electrically connected to a power input end. The first switch unit is electrically connected between the inductor and ground. The second switch unit is electrically connected between the inductor and an output end. The discharging loop is connected with the inductor in parallel and includes a third switch unit. The detecting circuit is used to detect a discharging value of the inductor. When the discharging value exceeds a threshold value, the third switch unit is turned on, and the inductor releases energy via the discharging loop.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: May 16, 2017
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Yue-Han Wu, Yii-Lin Wu, Ming-Ting Tsai, Kuan-Yi Lee
  • Patent number: 9384996
    Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Kun-Ju Li, Chang-Hung Kung, Yue-Han Wu, Chih-Chien Liu
  • Publication number: 20150340951
    Abstract: A boost converter and a power control method thereof. The boost converter includes an inductor, a first switch unit, a second switch unit, a discharging loop and a detecting circuit. The inductor is electrically connected to a power input end. The first switch unit is electrically connected between the inductor and ground. The second switch unit is electrically connected between the inductor and an output end. The discharging loop is connected with the inductor in parallel and includes a third switch unit. The detecting circuit is used to detect a discharging value of the inductor. When the discharging value exceeds a threshold value, the third switch unit is turned on, and the inductor releases energy via the discharging loop.
    Type: Application
    Filed: May 18, 2015
    Publication date: November 26, 2015
    Inventors: Yue-Han WU, Yii-Lin WU, Ming-Ting TSAI, Kuan-Yi LEE
  • Publication number: 20150325574
    Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Kun-Ju Li, Chang-Hung Kung, Yue-Han Wu, Chih-Chien Liu