Abstract: The present invention provides a method for constructing a fingerprint of a Xin Su Ning capsule and a fingerprint. The method includes: S1: taking contents of Xin Su Ning capsules of different batches, adding a methanol aqueous solution, and performing ultrasonic extraction to obtain test article solutions; S2: injecting the test article solutions into a high performance liquid chromatograph, performing gradient elution, performing chromatographic analysis, and recording chromatograms from 0 to 140 min; S3: importing the chromatograms into a traditional Chinese medicine chromatographic fingerprint similarity evaluation system to obtain a fingerprint; and S4: performing mass spectral analysis on the test article solutions, and determining chemical constituents of chromatographic peaks in the fingerprint according to results of the mass spectral analysis.

Abstract: The present invention is directed to a method for detecting somatic mutation in cell free total nucleic acid (cfTNA) in a liquid biological sample by a personalized approach with high sensitivity and specificity. The present invention relates to multiplex amplification of target loci with primers selected from a primer bank for cancer liquid biopsies, including but not limited to minimal residual disease (MRD) monitoring, recurrence monitoring, therapy monitoring, early detecting or screening cancer. Somatic, clonal variants of a patient are first identified by sequencing of the primary tumor and the matched normal sample in the patient. Then customized panel of primer pairs for the patient is selected from a primer bank. Using the selected panel of primer pairs, multiplex polymerase chain reaction and next-generation sequencing are performed on the cfTNA sample from this patient to detect the presence of tumor DNA in the sample.

Abstract: A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: A method of inspecting semiconductors and a semiconductor inspection system are disclosed. In an embodiment, the method comprises directing a charged particle beam onto a semiconductor device at an angle in a range between five degrees and eighty-five degrees from a normal to a top surface of the semiconductor; scanning the particle beam across a field of the semiconductor device; adjusting the semiconductor to maintain the particle beam at a defined focus on the semiconductor while scanning the particle beam across the field of the semiconductor device; detecting secondary and backscattered electrons from the semiconductor; and processing the detected secondary and backscattered electrons to inspect for defined conditions of the semiconductor. In an embodiment, the particle beam is maintained at the defined focus on the semiconductor device by controlling the position of the semiconductor device relative to a beam emitter that emits the particle beam.

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: Methods of fabricating integrated circuit devices for forming uniform and well controlled fin recesses are disclosed. One method includes, for instance: obtaining an intermediate semiconductor structure having a substrate, at least one fin disposed on the substrate, at least one gate structure positioned over the at least one fin, and at least one oxide layer disposed on the substrate and about the at least one fin and the at least one gate structure; implanting germanium (Ge) in a first region of the at least one fin; and removing the first region of the at least one fin implanted with Ge.

Abstract: A self-limiting selective epitaxy process can be employed on a plurality of semiconductor fins such that the sizes of raised active semiconductor regions formed by the selective epitaxy process are limited to dimensions determined by the sizes of the semiconductor fins. Specifically, the self-limiting selective epitaxy process limits growth of the semiconductor material along directions that are perpendicular to crystallographic facets formed during the selective epitaxy process. Once the crystallographic facets become adjoined to one another or to a dielectric surface, growth of the semiconductor material terminates, thereby preventing merger among epitaxially deposited semiconductor materials.

Abstract: Methods of forming a semiconductor fin and methods for controlling dopant diffusion to a semiconductor fin are disclosed herein. The methods provide alternative ways to incorporate a carbon dopant into the fin to later control out-diffusion of dopants from a dopant-including epitaxial layer. One method includes depositing a carbon-containing layer over a portion of the fin adjacent to the gate and annealing to diffuse carbon from the carbon-containing layer into at least the portion of the semiconductor fin. This method can be applied to SOI or bulk semiconductor substrates. Another method includes epitaxially growing a carbon dopant containing semiconductor layer for later use in forming the fin.

Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.