Abstract: A method for forming a conductive or magnetic pattern for a semiconductor or other electronic device includes patterning a mask layer outwardly from a conductive layer of the semiconductor device. The patterning defines portions of the conductive layer where vias through the conductive layer are desired. The method also includes exposing the semiconductor device to a plasma. The plasma converts the unmasked portions of the conductive layer into a compound. The method further includes exposing the semiconductor device to a treatment process to selectively remove the compound. The mask layer may be removed either before or after removal of the compound, thereby providing the unmasked conductive layer in the desired pattern.

Abstract: Forming an interconnect of a semiconductor device includes defining a recessed structure proximate to an outer surface of a substrate of a semiconductor device. A metal layer is deposited within the recessed structure. A region of the metal layer is exposed to a plasma operable to react with the region of the metal layer. A metal compound layer is formed from the region of the metal layer by reacting the region of the metal layer with the plasma. The metal compound layer is removed from the semiconductor structure to yield a remaining metal layer. An interconnect of the semiconductor device is formed from the remaining metal layer.

Abstract: A bipolar junction transistor includes a substrate, a first layer, a second layer, and a third layer. The first layer comprises non-single-crystalline semiconductor material having a first conductivity type deposited on the substrate. The second layer comprises non-single-crystalline semiconductor material having a second conductivity type deposited on at least a portion of the first layer. The third layer comprises non-single-crystalline semiconductor material having a conductivity type different than the second conductivity type deposited on at least a portion of the second layer. The first, second, and third layers form a collector, base, and emitter of the bipolar junction transistor.

Abstract: A method for forming a conductive or magnetic pattern for a semiconductor or other electronic device includes patterning a mask layer outwardly from a conductive layer of the semiconductor device. The patterning defines portions of the conductive layer where vias through the conductive layer are desired. The method also includes exposing the semiconductor device to a plasma. The plasma converts the unmasked portions of the conductive layer into a compound. The method further includes exposing the semiconductor device to a treatment process to selectively remove the compound. The mask layer may be removed either before or after removal of the compound, thereby providing the unmasked conductive layer in the desired pattern.

Abstract: A gate dielectric layer comprising a carbon film aligned to, and continuously covering, the gate electrode. The carbon dielectric film adheres to a wide variety of gate metals and is readily etched using etch processes which do not etch into the gate metal. In a preferred embodiment, the self-aligned carbon gate dielectric is deposited by plasma deposition, followed by deposition of a redundant gate dielectric.

Abstract: Polysilicon thin film transistors (TFTs) are formed on glass substrates by selectively etching a dielectric layer to expose portions of an amorphous silicon layer in areas of the substrate occupied by the thin film transistor forming a metal seed layer over the exposed portions of the amorphous silicon layer; and selectively annealing the exposed areas with a laser beam to transform the amorphous silicon layer to a polysilicon layer.

Abstract: A thin film transistor having two vertically stacked channels and dual gate non-photosensitive structure, where the source drain to bottom gate structure is self-aligned. This structure occupies the same area on a substrate as a conventional single gate thin film transistor. This invention also discloses a process for manufacturing a dual gate structure with a simple three mask procedure.

Abstract: A gate dielectric layer comprising a carbon film aligned to, and continuously covering, the gate electrode. The carbon dielectric film adheres to a wide variety of gate metals and is readily etched using etch processes which do not etch into the gate metal. In a preferred embodiment, the self-aligned carbon gate dielectric is deposited by plasma deposition, followed by deposition of a redundant gate dielectric.

Abstract: Horizontally redundant thin film transistors (TFTS) are disclosed having a U-shaped split gate with at least two elongated sections separated by a slit. Dielectric and semiconductor layers are respectively formed over the split gate. The semiconductor layer has redundant channels located over the split gate and separated by the slit. A common source is formed over the slit and is separated from at least two drains by the redundant channels. The drains are formed over an outer periphery of the elongated sections. The source and drains are self-aligned to the split gate to minimize the source-to-gate overlap. Source and drain contacts are formed over the source and drains, respectively. The horizontally redundant TFT also has dielectric sections formed over the semiconductor layer and aligned with the split gate. The horizontally redundant has large W/L and I.sub.on /I.sub.off ratios, and occupies a small area, which are particularly useful featutes in forming high quality displays.

Abstract: A thin film transistor having two vertically stacked channels and dual gate non-photosensitive structure, where the source drain to bottom gate structure is self-aligned. This structure occupies the same area on a substrate as a conventional single gate thin film transistor. This invention also discloses a process for manufacturing a dual gate structure with a simple three mask procedure.

Abstract: A method of low temperature and rapid silicon crystallization or rapid transformation of amorphous silicon to high quality polysilicon over a large area is disclosed using a pulsed rapid thermal annealing (PRTA) method and a metal seed layer. The PRTA method forms polysilicon thin film transistors (TFTs) with a high throughput, on low temperature and large area glass substrates. The PRTA method includes the steps of forming over a glass layer a tri-layer structure having a layer of amorphous silicon sandwiched between bottom and top dielectric layers; selectively etching the top dielectric layer to expose portions of the amorphous silicon layer; forming a metal seed layer over the exposed portions of the amorphous silicon layer; and pulsed rapid thermal annealing using successive pulses separated by rest periods to transform the amorphous silicon layer to a polysilicon layer. In an alternate PRTA method, instead of forming the tri-layer structure, a bi-layer structure is formded over the glass layer.

Abstract: An improved method for coating a semiconductor wafer with a uniform layer of photoresist or other liquid film is provided. The liquid is first semi-uniformly deposited on the wafer by spraying or otherwise. Thereafter, the wafer is rotated about an axis perpendicular to the plane of the wafer and removed from the wafer. In the preferred embodiment, a number of wafers are placed about the perimeter of a large, flat disc which is rotated about its center. The liquid is spread over the surface of each wafer by the centrifugal force generated by such rotation. By placing the wafers at a distance from the axis of rotation, the centrifugal force on all points of each wafer is approximately the same, thereby providing for a uniform spreading of the film over the wafer.