Abstract: A device includes a first transistor and a second transistor. The first transistor includes a first gate terminal coupled to the first source terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal coupled to the first drain terminal, a second source terminal, and a second drain terminal.

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a barrier layer disposed on the buffer layer, a source, a drain, and a gate stack. The source, the drain, and the gate stack are disposed on the barrier layer. The gate stack includes a first epitaxial layer on the barrier layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The semiconductor device further includes a gate disposed on the gate stack.

Abstract: A device includes a first transistor and a second transistor. The first transistor includes a first gate terminal coupled to the first source terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal coupled to the first drain terminal, a second source terminal, and a second drain terminal.

Abstract: A nitride-based semiconductor device is disclosed, including a substrate, an active region including a plurality of nitride-based semiconductor layers disposed on the substrate, wherein a 2DEG channel and a two-dimensional hole gas (2DHG) under the two-dimensional electron gas (2DEG) channel are formed within the plurality of nitride-based semiconductor layers, a gate electrode disposed on the top of the active region and an interconnection structure electrically connected with the gate electrode and the 2DHG.

Abstract: A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced.

Abstract: A lateral avalanche photodiode structure including a substrate, a PN diode and a metal layer is provided. The substrate has at least one first electrode area, at least one light receiving area, and at least one second electrode area which are arranged horizontally. The first electrode area is also an avalanche area, and the light receiving area is between the first electrode area and the second electrode area. The PN diode is disposed in the substrate in the first electrode area. The metal layer is disposed on the substrate and covers the first electrode area and the second electrode area, but does not cover the light receiving area.

Abstract: A lateral avalanche photodiode structure including a substrate, a PN diode and a metal layer is provided. The substrate has at least one first electrode area, at least one light receiving area, and at least one second electrode area which are arranged horizontally. The first electrode area is also an avalanche area, and the light receiving area is between the first electrode area and the second electrode area. The PN diode is disposed in the substrate in the first electrode area. The metal layer is disposed on the substrate and covers the first electrode area and the second electrode area, but does not cover the light receiving area.

Abstract: A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced.

Abstract: A silicon photo-detection module is disclosed, in which a silicon photodiode detection unit and a parasitical vertical bipolar junction transistor amplification unit can be simultaneously formed by a CMOS process. The silicon photo-detection module has a silicon substrate, a silicon photodiode detection unit comprising a positive portion and a negative portion, and a parasitical vertical bipolar junction transistor amplification unit comprising a collector, a base, and an emitter. The silicon photodiode detection unit and the parasitical vertical bipolar junction transistor amplification unit are formed on the silicon substrate by a CMOS process. Besides, the positive and negative portions of the silicon photodiode detection unit are electrically connected respectively with the base and the collector of the parasitical vertical bipolar junction transistor amplification unit.

Abstract: A fluorescence detection system for measuring biomolecules is disclosed, which includes a fluorescence detection device, a light source, a sample-loading unit, and an analysis-reading device. The fluorescence detection device has a substrate and plural phototransistors arranged on the substrate, and each phototransistor contains an emitter, a collector locating on the substrate, and a base between the emitter and the collector. The base-collector diode junction functions as an absorber to convert fluorescence to photocurrent. The light source serves to excite a fluorescent dye contained in a biomolecule sample. The sample-loading unit is used to load or transport the excited biomolecule sample onto a sensing zone of the fluorescence detection device. The analysis-reading device is to measure photocurrent output from the fluorescence detection device under a bias. Hence, the biomolecule content can be easily determined by the fluorescence detection system.

Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Abstract: A gallium nitride heterojunction bipolar transistor with a p-type strained InGaN base layer is provided. The gallium nitride heterojunction bipolar transistor includes a substrate, a highly doped collector contact layer located over the substrate, a low doped collector layer located over the collector contact layer, a p-type base layer located over the collector layer, a highly doped strained InGaN base layer located over the p-type base layer, a emitter layer located over the p-type strained InGaN base layer, a highly doped emitter contact layer located over the emitter layer, and an emitter metal electrode, a base metal electrode, and a collector metal electrode respectively located on the emitter contact layer, the p-type strained InGaN base layer, and the collector contact layer.

Abstract: A structure of a silicon photodetector and a method for forming the same by using the conventional CMOS semiconductor manufacturing process and micro-electromechanical system manufacturing process, in which the micro-electromechanical system manufacturing process (lateral etching process) is applied for elimination of effect and interference caused by a substrate of the silicon photodetector after optical absorption thereof, thereby greatly improving the response speed of the silicon photodetector. This can be done only by applying the lateral etching process onto a portion of the substrate of the silicon photodetector after the semiconductor manufacturing process is finished, through which slow diffusion carriers produced from the optical absorption of the substrate can be effectively reduced and the response speed is thus enhanced.

Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Abstract: A gallium nitride heterojunction bipolar transistor with a p-type strained InGaN base layer is provided. The gallium nitride heterojunction bipolar transistor includes a substrate, a highly doped collector contact layer located over the substrate, a low doped collector layer located over the collector contact layer, a p-type base layer located over the collector layer, a highly doped strained InGaN base layer located over the p-type base layer, a emitter layer located over the p-type strained InGaN base layer, a highly doped emitter contact layer located over the emitter layer, and an emitter metal electrode, a base metal electrode, and a collector metal electrode respectively located on the emitter contact layer, the p-type strained InGaN base layer, and the collector contact layer.