Abstract: Impulse noise from nearby or intense electrical sources can disrupt communications over digital subscriber lines. There are many methods to deal with errors produced by impulse noise sources. Forward error correction (FEC) codes such as Reed Solomon coding along with scrambling and interleaving are used to correct small errors. However, for larger errors, retransmission is favored. Retransmission can be applied at the Discrete Multi-tone symbol level thus eliminating the need to insert sequence identification into data transmission units, furthermore retransmission can also be employed to exploit the error correcting capabilities of the FEC codes. Finally, an impulse noise protection system can exploit impulse noise statistics to configure the redundancy in the FEC codes and to enable the use of blanking. Exemplary embodiments of systems described can cooperatively use impulse noise statistics to utilize retransmission, FEC and blanking to mitigate the effects of impulse noise.

Abstract: Various embodiments for mitigating impulse noise are disclosed that cooperatively use impulse noise statistics to utilize retransmission, forward error correction (FEC), and blanking to mitigate the effects of a wide variety of impulse noise sources.

Abstract: Impulse noise from nearby or intense electrical sources can disrupt communications over digital subscriber lines. There are many methods to deal with errors produced by impulse noise sources. Forward error correction (FEC) codes such as Reed Solomon coding along with scrambling and interleaving are used to correct small errors. However, for larger errors, retransmission is favored. Retransmission can be applied at the Discrete Multi-tone symbol level thus eliminating the need to insert sequence identification into data transmission units, furthermore retransmission can also be employed to exploit the error correcting capabilities of the FEC codes. Finally, an impulse noise protection system can exploit impulse noise statistics to configure the redundancy in the FEC codes and to enable the use of blanking. Exemplary embodiments of systems described can cooperatively use impulse noise statistics to utilize retransmission, FEC and blanking to mitigate the effects of impulse noise.

Abstract: Impulse noise from nearby or intense electrical sources can disrupt communications over digital subscriber lines. There are many methods to deal with errors produced by impulse noise sources. Forward error correction (FEC) codes such as Reed Solomon coding along with scrambling and interleaving are used to correct small errors. However, for larger errors, retransmission is favored. Retransmission can be applied at the Discrete Multi-tone symbol level thus eliminating the need to insert sequence identification into data transmission units, furthermore retransmission can also be employed to exploit the error correcting capabilities of the FEC codes. Finally, an impulse noise protection system can exploit impulse noise statistics to configure the redundancy in the FEC codes and to enable the use of blanking. Exemplary embodiments of systems described can cooperatively use impulse noise statistics to utilize retransmission, FEC and blanking to mitigate the effects of impulse noise.

Abstract: Systems and methods for a memory structure are described for increasing the throughput of double precision operations. Broadly, the present invention utilizes a novel memory system to process double precision data in a single memory access. In accordance with one embodiment, a method for increasing throughput of arithmetic operations on double precision data by reducing the number of memory accesses comprising: retrieving a double precision value from a memory, wherein the double precision value is comprised of a high word and a low word, wherein the double precision value is retrieved in a single memory access; selecting a word within the double precision value, wherein the portion selected is a single precision value; multiplying the word with a single precision operand to generate a single precision product; adding the product to a double precision operand to produce a double precision result; and forwarding the double precision result back to memory for storage.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: A processing circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a data pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Abstract: The present invention is generally directed to a processing circuit for computing a fast Fourier transform (FFT). The present invention reflects the recognition that excessive reads to and writes from memory consume excessive amounts of power. Accordingly, the circuit of the present is specifically designed to minimize the number of reads and writes to memory. In addition, the circuit is designed so that processing parallelism may be achieved in order to reduce the total number of clock cycles required to compute a FFT. In accordance with one aspect of the invention, the processing circuit includes a data memory for storing data values, and a separate coefficient memory for storing coefficient (or twiddle) values. The circuit further includes a multiplier configured to multiply values received from the coefficient memory and another value retrieved from some other location.

Abstract: The present invention is generally directed to a processing circuit for computing a fast Fourier transform (FFT). The present invention reflects the recognition that memory space for the storage of symmetrical coefficients can be realized by storing the coefficients associated with one complex number in order to generate eight related complex numbers. Accordingly, the circuit of the present invention is specifically designed to minimize the coefficient memory requirements for symmetrical coefficients.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: A process circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a date pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Abstract: Disclosed is an RS decoder controller and method, the system comprising a codeword length register to indicate a number of symbols in a number of RS codewords to be decoded by the RS decoder, a error correction capability configuration register to indicate a number of error symbols that are corrected by the RS decoder, and a modulation scheme associated register to indicate a modulation scheme associated employed to generate the RS codewords. The RS decoder controller further includes a number of state machines to control the operation of a Galois field computation unit in the RS decoder.

Abstract: Disclosed is a configurable Galois field computation system and method, the system comprising a read bus and a write bus with a memory coupled therebetween. In addition, a logical circuit is coupled between the read and write busses, the logical circuit having a number of data calculation configurations that are established to generate an n symbol codeword from a number of symbols in a syndrome array. The logical circuit is placed in the various data calculation configurations in order to perform the various operations involved with Reed-Solomon decoding.

Abstract: Disclosed is a configurable Reed-Solomon (RS) decoder that comprises a parallel multiply accumulator having a data input to receive at least one RS codeword, the parallel multiply accumulator being configured to generate a syndrome array from the RS codeword. The configurable RS decoder also includes a Galois field computation unit coupled to the parallel multiply accumulator, and an RS decoder controller coupled to the parallel multiply accumulator and the Galois field computation unit, wherein the RS decoder controller controls the operation of the parallel multiply accumulator and the Galois field computation unit. The RS decoder may be configured for different numbers of symbols in the RS codewords, parity symbols in the RS codewords, and modulation types employed in creating the RS codewords.

Abstract: Disclosed is a configurable Reed-Solomon encoder and method. The configurable Reed-Solomon encoder comprises a multiplexed multiplier-accumulator, a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer. The configurable Reed-Solomon encoder is preferably implemented in an application specific integrated circuit (ASIC), although it may be implemented in software executed by a high-speed digital signal processor, etc.

Abstract: An integrated circuit for processing a speech signal in accordance with a CELP standard includes a plurality of processing elements coupled to a data bus in parallel. Each processing element includes a multiplier and an accumulator. The integrated circuit further includes an auxiliary processing element, which is also coupled to the data bus and has a division unit and a comparator. The plurality of processing elements and the auxiliary processing element are also coupled in a pipeline formation.