Abstract: Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located within the housing and electrically coupled to the package contact (104). The dies (106) of the first and second modules dies are configured to store a module configuration state. The first and second modules (107a, 107b) are enabled for operation based, at least in part, on the reclamation state and the module configuration state.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a target memory cell of the memory cells into one of x intermediate levels based on all pages of N pages of the piece of N-bits data to be stored in the target memory cell, where x is an integer smaller than 2N. The peripheral circuit is also configured to program, in a second pass after the first pass, the target memory cell into one of the 2N levels based on all pages of the N pages of the piece of N-bits data to be stored in the target memory cell.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each of the row of target memory cells is programmed into one of 2N/m intermediate levels based on the piece of N-bits data to be stored in the target memory cell, where m is an integer greater than 1. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2N levels based on the piece of N-bits data to be stored in the target memory cell.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each of the row of target memory cells is programmed into one of 2N/m intermediate levels based on the piece of N-bits data to be stored in the target memory cell, where m is an integer greater than 1. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2N levels based on the piece of N-bits data to be stored in the target memory cell.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.

Abstract: A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list, generating the full-coverage input stimuli according to the analog constraint, performing a behavioral-level simulation using the full-coverage input stimuli and according to the behavioral code to generate a behavioral-level simulation result, performing a circuit-level simulation using the full-coverage input stimuli and according to the circuit-level netlist to generate a circuit-level simulation result, and comparing the behavioral-level simulation result and the circuit-level simulation result to generate a comparison report for an analog value auto-comparison.

Abstract: An integration method for a 3D NAND flash memory device includes disposing a plurality of 3D triple-level cell (TLC) NAND flash memories on a CMOS die; disposing at least a NOR Flash memory on the CMOS die of the 3D NAND flash memory device; and connecting the at least a NOR Flash memory to an Open NAND Flash Interface (ONFI) of the 3D NAND flash memory device; wherein the at least a NOR Flash memory is disposed on an unused area of the CMOS die.

Abstract: A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list, generating the full-coverage input stimuli according to the analog constraint, performing a behavioral-level simulation using the full-coverage input stimuli and according to the behavioral code to generate a behavioral-level simulation result, performing a circuit-level simulation using the full-coverage input stimuli and according to the circuit-level netlist to generate a circuit-level simulation result, and comparing the behavioral-level simulation result and the circuit-level simulation result to generate a comparison report for an analog value auto-comparison.

Abstract: Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located within the housing and electrically coupled to the package contact (104). The dies (106) of the first and second modules dies are configured to store a module configuration state. The first and second modules (107a, 107b) are enabled for operation based, at least in part, on the reclamation state and the module configuration state.

Abstract: Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located within the housing and electrically coupled to the package contact (104). The dies (106) of the first and second modules dies are configured to store a module configuration state. The first and second modules (107a, 107b) are enabled for operation based, at least in part, on the reclamation state and the module configuration state.

Abstract: Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located within the housing and electrically coupled to the package contact (104). The dies (106) of the first and second modules dies are configured to store a module configuration state. The first and second modules (107a, 107b) are enabled for operation based, at least in part, on the reclamation state and the module configuration state.

Abstract: Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located within the housing and electrically coupled to the package contact (104). The dies (106) of the first and second modules dies are configured to store a module configuration state. The first and second modules (107a, 107b) are enabled for operation based, at least in part, on the reclamation state and the module configuration state.

Abstract: Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located within the housing and electrically coupled to the package contact (104). The dies (106) of the first and second modules dies are configured to store a module configuration state. The first and second modules (107a, 107b) are enabled for operation based, at least in part, on the reclamation state and the module configuration state.