Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a carbon nanotube structure, a source electrode and a drain electrode. The gate insulating layer is located on the gate electrode. The carbon nanotube structure is located on the gate insulating layer. The source electrode and the drain electrode are arranged at intervals and electrically connected to the carbon nanotube structure respectively. The thin film transistor further includes an interface charge layer, and the interface charge layer is located between the carbon nanotube structure and the gate insulating layer.

Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.

Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).

Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.

Abstract: A display substrate, a display device and a wireless charging method are provided. The display substrate includes: a display area and a peripheral area located outside the display area. The peripheral area includes a circuit binding area. The display substrate includes a base substrate and a wireless charging antenna disposed on the base substrate. The wireless charging antenna includes a power receiving coil and a connection lead. The connection lead is connected to the power receiving coil, and the power receiving coil is connected to the circuit binding area.

Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.

Abstract: The present disclosure provides a shift register unit whose operating time includes a plurality of multi-frame periods, each of the multi-frame periods including a plurality of frame periods. The shift register unit includes a trigger signal input terminal, an input module, a pull-up module, a pull-down control module, a plurality of pull-down modules, and a signal output terminal. The pull-down control module is configured to sequentially provide active signals to the control terminals of respective pull-down modules in pull-down stages of respective frame periods of one multi-frame period. The present disclosure further provides a shift register, a gate driving circuit and a display panel. The shift register unit has longer lifetime and better electric performance, and can meet the requirements of high-reliability products.

Abstract: A shift register and a corresponding driving method, a gate driving circuit and a display device, the shift registers includes an input and reset circuit, a first output circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit; the first output circuit and the second output circuit output gate driving signals according to potentials at a first clock signal terminal and a second clock signal terminal respectively, the first pull-down circuit and the second pull-down circuit reset potentials at a pull up node, a first output terminal and a second output terminal according to potentials at a first pull-down node a second pull-down node respectively.

Abstract: The present disclosure provides a shift register unit whose operating time includes a plurality of multi-frame periods, each of the multi-frame periods including a plurality of frame periods. The shift register unit includes a trigger signal input terminal, an input circuit, a pull-up circuit, a pull-down control circuit, a plurality of pull-down circuits, and a signal output terminal. The pull-down control circuit is configured to sequentially provide active signals to the control terminals of respective pull-down circuits in pull-down stages of respective frame periods of one multi-frame period. The present disclosure further provides a shift register, a gate driving circuit and a display panel.

Abstract: A shift register and a corresponding driving method, a gate driving circuit and a display device, the shift registers includes an input and reset circuit, a first output circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit; the first output circuit and the second output circuit output gate driving signals according to potentials at a first clock signal terminal and a second clock signal terminal respectively, the first pull-down circuit and the second pull-down circuit reset potentials at a pull up node, a first output terminal a second output terminal according to potentials at a first pull-down node a second pull-down node respectively.

Abstract: A display substrate, a display device and a wireless charging method are provided. The display substrate includes: a display area and a peripheral area located outside the display area. The peripheral area includes a circuit binding area. The display substrate includes a base substrate and a wireless charging antenna disposed on the base substrate. The wireless charging antenna includes a power receiving coil and a connection lead. The connection lead is connected to the power receiving coil, and the power receiving coil is connected to the circuit binding area.

Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.

Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.

Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.

Abstract: A method of manufacturing Ce:YAG polycrystalline phosphor with the formula (Y1-x-mAxCem)3(Al1-yBy)5O12; 0?x?1, 0?y?1, 0?m?0.05; wherein A is one of Lu, Tb, Pr, La and Gd; and wherein B is one of Ga, Ti, Mn, Cr and Zr.

Abstract: The present invention relates to a novel white light LED packaging structure and a process for manufacturing the same. An anti-blue light reflection film(s) is deposited on one surface of a fluorescent wafer, wherein the surface is attached to a blue-emitting chip. The anti-blue light reflection film(s) on the wafer can effectively prevent the incident blue light from reflecting on the surface of the wafer, increase the availability of the blue light and reduce the reflection loss of yellowish green light in the direction towards the chip, and thereby improving the whole luminous efficacy of the device. The white light LED packaging structure of the present invention has high fluorescence efficiency, and is suitable for applying in high-power white light LED illumination field.

Abstract: The present invention relates to a white light LED lamp and a filament. The white light LED filament comprises light emitting units and a strip-shaped fluorescent wafer(s) at least positioned at one side of the light emitting units, wherein the light emitting units are blue-emitting chips connected by a metal wire or an electric conductive circuit, and wherein electrodes are arranged at the end(s) of the fluorescent wafer. Without any lens, the filament of the present invention has a simple structure. A white light LED lamp using the filament realizes a 360° stereo-luminescence, and shows the advantages of low cost, excellent heat radiation, high luminous efficacy and so on.

Abstract: The present invention relates to a Ce:YAG wafer-based composite structure comprising a Ce:YAG wafer and a red light emitting layer fixed on the Ce:YAG wafer. The present invention also relates to a method for the preparation of the Ce:YAG wafer-based composite structure. The optical composite structure realizes a wide waveband luminescence from green light to red light, and can be widely used in the fields of detection equipment and illumination devices.