Patents by Inventor Yue Tan
Yue Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964464Abstract: A tape includes: a substrate, a conductive adhesive layer disposed on the substrate, and an insulating layer disposed on a part of a bonding surface of the conductive adhesive layer. The insulating layer is configured to insulate the conductive adhesive layer from a conducting part of an object to be bonded.Type: GrantFiled: October 29, 2019Date of Patent: April 23, 2024Assignees: Beijing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Dong Cui, Rui Han, Qing Ma, Zeyuan Tong, Zhipeng Zhang, Fengping Wang, Yue Zhai, Zan Zhang, Wenyang Li, Weining Chi, Rui Tan, Shouyang Leng
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Publication number: 20240066112Abstract: Provided is a GII.4 norovirus virus-like particle or active fragment thereof, and use thereof, the virus-like particle comprising or being composed of an amino acid sequence shown as SEQ ID NO: 4. Further, provided is a composition or a kit comprising the GII.4 norovirus virus-like particle, and use thereof. The objective of covering multiple genotypes is achieved by using a single antigen of the invention, the process difficulty of the preparation for a pharmaceutical composition or a vaccine can be reduced, and the production cost is decreased. Also, provided is a norovirus immune composition or a kit comprising GII.2, GII.4, GII.6, and GII.17 norovirus virus-like particles or active fragments thereof, and use thereof.Type: ApplicationFiled: December 21, 2021Publication date: February 29, 2024Applicant: GRAND THERAVAC LIFE SCIENCE (NANJING) CO., LTD.Inventors: Jianqiang Li, Jun Ge, Xiaodong Wang, Changyao Tan, Sulin Ren, Tong Zhou, Yue Gu, Yue Chen, Hongying Huang, Xiaoxiao Chen
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Publication number: 20150115365Abstract: Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.Type: ApplicationFiled: January 5, 2015Publication date: April 30, 2015Inventors: Dechao Guo, Yang Liu, Chengwen Pei, Yue Tan
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Patent number: 8927432Abstract: Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.Type: GrantFiled: June 14, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Dechao Guo, Yang Liu, Chengwen Pei, Yue Tan
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Publication number: 20140264444Abstract: Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench isolation structure. A shallow trench isolation (STI) spacer is formed on sidewalls of the shallow trench isolation structure around the periphery of the active area. After formation of a gate stack structure and a gate spacer, trenches are formed such that sidewalls of the trenches are vertically coincident with sidewalls of the gate spacer and the STI spacer. Epitaxial semiconductor material can be deposited into the trenches by selective epitaxy to form an embedded source region and an embedded drain region. Because all surfaces of the trenches are semiconductor surfaces, the entire trenches can be filled with the epitaxial semiconductor material, thereby enabling lateral confinement of stress within a channel region of a field effect transistor.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Dechao Guo, Yang Liu, Chengwen Pei, Yue Tan
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Patent number: 8809187Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.Type: GrantFiled: September 14, 2012Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Yue Tan, Zhibin Ren, Richard A. Wachnik, Haining S. Yang
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Publication number: 20140027851Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.Type: ApplicationFiled: September 14, 2012Publication date: January 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yue Tan, Zhibin Ren, Richard A. Wachnik, Haining S. Yang
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Publication number: 20130334602Abstract: Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.Type: ApplicationFiled: June 14, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Yang Liu, Chengwen Pei, Yue Tan
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Patent number: 8338292Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.Type: GrantFiled: February 17, 2010Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Yue Tan, Zhibin Ren, Richard A. Wachnik, Haining S. Yang
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Patent number: 8207027Abstract: A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.Type: GrantFiled: October 22, 2009Date of Patent: June 26, 2012Assignee: International Business Machines CorporationInventors: Huilong Zhu, Yue Tan
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Publication number: 20100207213Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.Type: ApplicationFiled: February 17, 2010Publication date: August 19, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yue Tan, Zhibin Ren, Richard A. Wachnik, Haining S. Yang
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Patent number: 7768816Abstract: A design structure embodied in a machine readable medium for use in a design process, the design structure representing a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, the SRAM cell is an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, the SRAM cell is a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions.Type: GrantFiled: December 7, 2007Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Yue Tan, Robert C. Wong
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Patent number: 7755926Abstract: A design structure for a three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a type of sense amplifier on an additional chips or chips overlying the memory array. Freedom of placement of such peripheral circuits is provided with minimal increase in connection length since word line decoders may be placed is general registration with any location along the word lines while local evaluation circuits and/or sense amplifiers can be placed at any location generally in registration with the bit line(s) to which they correspond.Type: GrantFiled: October 5, 2007Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Yue Tan, Huilong Zhu
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Publication number: 20100041198Abstract: A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.Type: ApplicationFiled: October 22, 2009Publication date: February 18, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huilong Zhu, Yue Tan
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Patent number: 7655989Abstract: A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.Type: GrantFiled: November 30, 2006Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Yue Tan
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Publication number: 20090147560Abstract: A design structure embodied in a machine readable medium for use in a design process, the design structure representing a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, the SRAM cell is an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, the SRAM cell is a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions.Type: ApplicationFiled: December 7, 2007Publication date: June 11, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rajiv V. Joshi, Yue Tan, Robert C. Wong
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Publication number: 20080310220Abstract: A three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a type of sense amplifier on an additional chips or chips overlying the memory array. Freedom of placement of such peripheral circuits is provided with minimal increase in connection length since word line decoders may be placed is general registration with ant location along the word lines while local evaluation circuits and/or sense amplifiers can be placed at any location generally in registration with the bit line(s) to which they correspond.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yue Tan, Huilong Zhu
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Publication number: 20080310207Abstract: A design structure for a three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a type of sense amplifier on an additional chips or chips overlying the memory array. Freedom of placement of such peripheral circuits is provided with minimal increase in connection length since word line decoders may be placed is general registration with ant location along the word lines while local evaluation circuits and/or sense amplifiers can be placed at any location generally in registration with the bit line(s) to which they correspond.Type: ApplicationFiled: October 5, 2007Publication date: December 18, 2008Inventors: Yue Tan, Huilong Zhu
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Publication number: 20080128796Abstract: A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.Type: ApplicationFiled: November 30, 2006Publication date: June 5, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huilong Zhu, Yue Tan
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Patent number: 7355906Abstract: A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions. Both methods improve stability by eliminating half-select mode and facilitate rail to rail data transfer in and out of the SRAM cell without disturbing the other cells.Type: GrantFiled: May 24, 2006Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Yue Tan, Robert C. Wong