Abstract: The present disclosure generally relates to methods and user interfaces for authentication, including providing authentication at a computer system in accordance with some embodiments.

Abstract: A 3D-configured production structure of rubber products based on an intelligent manufacturing unit and a production method thereof. The structure includes a stereoscopic production warehouse used to store a mobile intelligent manufacturing unit and an ex-warehouse delivery system used to deliver the mobile intelligent manufacturing unit. The mobile intelligent manufacturing unit includes a unit functional assembly, a molding vulcanization apparatus, a blank feeder, a material-delivering apparatus, a product-collecting apparatus and a reclaimer. The molding vulcanization apparatus includes a upper heat plate, a upper mold, a lower mold, a lower heat plate and a support post. The upper mold and the lower mold are arranged on the inner sides of the upper heat plate and the lower heat plate, respectively. The upper heat plate is fixed on one end of the support post, and the lower heat plate is arranged through the support post.

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.

Abstract: Techniques for video communications include: transmitting, from a first apparatus, a first video stream of a first user to a second apparatus of a second user; receiving, from the second apparatus, a second video stream of the second user; determining a reaction of the second user to an area of interest in the first video stream using the second video stream; and updating a parameter for encoding the area of interest in the first video stream based on the reaction of the second user to the area of interest in the first video stream, and one or more tags associated with the reaction of the second user are used to train an adaptive encoder to automatically adjust the parameter for encoding the area of interest in the first video stream to optimize video viewing experiences based on the reaction of the second user.

Abstract: The present invention relates to a base station for a cleaning robot to park in, where the cleaning robot includes a wiping board, and a flexible wiping member replaceably butts the wiping board to form a wiping surface to wipe a working surface on which the cleaning robot walks, where the base station includes: a storage module, configured to store a continuous wiping base material; and a feeding module, configured to drive a free end of the wiping base material to be conveyed to a cutting position, to cause the free end to be cut from the wiping base material to form the wiping member. The present invention has the following beneficial effects: After returning to the base station, the cleaning robot may automatically mount a wiping member without intervention by a user.

Abstract: The present disclosure generally relates to methods and user interfaces for authentication, including providing authentication at a computer system in accordance with some embodiments.

Abstract: A method, an apparatus, and a system for video communications include: transmitting, from a first apparatus using a network, a first video stream of a first user to a second apparatus of a second user, wherein the first user is in video communication with the second user; receiving, from the second apparatus using the network, a second video stream of the second user; determining, by a processor, a reaction of the second user to an area of interest in the first video stream using the second video stream; and updating, in response to the reaction of the second user to the area of interest in the first video stream, a parameter for encoding the area of interest in the first video stream at the first apparatus.

Abstract: Described herein are integrated circuit devices that include both nanoribbon-based transistors and fin-shaped transistors. The nanoribbon transistors may have shorter channel lengths than the fin transistors. In addition, the nanoribbon transistors may have thinner gate dielectrics than the fin transistors.

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.

Abstract: Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance inductance capacitance (RLC) circuit to provide ESD stimulus to the DUT. The ESD stimulus and therefore the test bench may be based on a human body model (HBD) or a charged device model (CDM). In case of the CDM, the computer may allow a circuit designer to select or deselect package parameters for testing the ESD protection circuit.

Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.

Abstract: A friction hinge with its motion restricted in one pivoting direction includes a support member, a restricting module, and a pivot member. The restricting module is mounted on the support member. The restricting module has an air flow opening. The pivot member is pivotable relative to the support member and the restricting module. A regulating chamber is defined between the pivot member and the restricting module. When the pivot member is pivoted in one direction, a pressure in the regulating chamber is increased and the restricting module is actuated to reduce size of the air flow opening, increasing the resistance to pivoting of the pivot member in this pivoting direction.

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities.