Abstract: Embodiments of the invention provide increased ESD protection suitable for high-voltage devices. In one embodiment, an internal DMOS circuit is placed in parallel with a lateral NPN ESD clamp. The clamp has both a high holding voltage, above the operating voltage of the DMOS circuit, and a high maximum current before breakdown. The discharge path of the clamp includes a high-voltage lightly doped well containing a low-voltage higher doped well. The dopant of both wells is the same type, and the interface between the two defines a graded junction. The emitter of the entire circuit is grounded and the collector is coupled to the voltage of the DMOS circuit.