Patents by Inventor Yuedong QIU
Yuedong QIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971467Abstract: A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.Type: GrantFiled: February 3, 2020Date of Patent: April 6, 2021Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventors: Yuedong Qiu, ChengChung Lin
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Publication number: 20200176410Abstract: A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.Type: ApplicationFiled: February 3, 2020Publication date: June 4, 2020Inventors: Yuedong Qiu, ChengChung Lin
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Patent number: 10593641Abstract: A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.Type: GrantFiled: May 20, 2016Date of Patent: March 17, 2020Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventors: Yuedong Qiu, Chengchung Lin
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Patent number: 10553458Abstract: The method of chip packaging comprises: S1: providing a carrier, and forming an adhesive layer on a surface of the carrier; S2: forming a first dielectric layer on a surface of the adhesive layer, and forming a plurality of first through holes corresponding to electrical leads of a semiconductor chip in the dielectric layer; S3: attaching the semiconductor chip with the front surface facing downwards to the surface of the first dielectric layer; S4: forming a plastic encapsulation layer covering the chip on the surface of the first dielectric layer; S5: separating the adhesive layer and the first dielectric layer to remove the carrier and the adhesive layer; and S6: forming a redistribution layer for the semiconductor chip based on the first dielectric layer and the first through holes.Type: GrantFiled: May 20, 2016Date of Patent: February 4, 2020Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventors: Yuedong Qiu, Chengchung Lin
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Patent number: 10290515Abstract: A wafer level chip packaging method, comprising: 1) providing a carrier and forming a bonding layer on a surface of the carrier; 2) forming a dielectric layer on a surface of the bonding layer; 3) attaching each of semiconductor chips, with its front face facing down, to a surface of the dielectric layer; 4) packaging each of the semiconductor chips by using an injection molding process; 5) separating the bonding layer and the dielectric layer to remove the carrier and the bonding layer; 6) forming a redistribution layer for the semiconductor chips based on the dielectric layer; and 7) performing a reballing reflow process on the redistribution layer to form micro bumps. As a result, contamination in the semiconductor chips from the packaging process is greatly controlled, thereby improving the rate of finished products and the electrical property of the semiconductor chips.Type: GrantFiled: May 20, 2016Date of Patent: May 14, 2019Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventors: Chengchung Lin, Yuedong Qiu
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Publication number: 20190035642Abstract: The method of chip packaging comprises: S1: providing a carrier, and forming an adhesive layer on a surface of the carrier; S2: forming a first dielectric layer on a surface of the adhesive layer, and forming a plurality of first through holes corresponding to electrical leads of a semiconductor chip in the dielectric layer; S3: attaching the semiconductor chip with the front surface facing downwards to the surface of the first dielectric layer; S4: forming a plastic encapsulation layer covering the chip on the surface of the first dielectric layer; S5: separating the adhesive layer and the first dielectric layer to remove the carrier and the adhesive layer; and S6: forming a redistribution layer for the semiconductor chip based on the first dielectric layer and the first through holes.Type: ApplicationFiled: May 20, 2016Publication date: January 31, 2019Applicant: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventors: Yuedong QIU, Chengchung LIN
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Publication number: 20190006307Abstract: A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.Type: ApplicationFiled: May 20, 2016Publication date: January 3, 2019Inventors: Yuedong QIU, Chengchung LIN
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Publication number: 20180240683Abstract: A wafer level chip packaging method, comprising: 1) providing a carrier and forming a bonding layer on a surface of the carrier; 2) forming a dielectric layer on a surface of the bonding layer; 3) attaching each of semiconductor chips, with its front face facing down, to a surface of the dielectric layer; 4) packaging each of the semiconductor chips by using an injection molding process; 5) separating the bonding layer and the dielectric layer to remove the carrier and the bonding layer; 6) forming a redistribution layer for the semiconductor chips based on the dielectric layer; and 7) performing a reballing reflow process on the redistribution layer to form micro bumps. As a result, contamination in the semiconductor chips from the packaging process is greatly controlled, thereby improving the rate of finished products and the electrical property of the semiconductor chips.Type: ApplicationFiled: May 20, 2016Publication date: August 23, 2018Inventors: Chengchung LIN, Yuedong QIU