Abstract: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs respectively associated with a plurality of first electrical contacts. A first spacing of the plurality of first electrical contacts may define a first pitch. The emitter assembly may include a redistribution layer, disposed on the VCSEL chip, to increase the first pitch of the plurality of first electrical contacts. The emitter assembly may include a carrier having a plurality of second electrical contacts. A second spacing of the plurality of second electrical contacts may define a second pitch greater than the first pitch. The emitter assembly may include a plurality of conductive pillars that electrically connect the plurality of first electrical contacts and the plurality of second electrical contacts via the redistribution layer. The plurality of conductive pillars may be arranged according to the second spacing.

Abstract: In some implementations, a vertical cavity surface emitting laser (VCSEL) device may include a substrate, and a set of epitaxial layers, disposed on the substrate, defining a plurality of VCSEL mesa structures, where each of the plurality of VCSEL mesa structures has a top surface and a sidewall. The VCSEL device may include an additional layer structure disposed on the set of epitaxial layers, where the additional layer structure configures the plurality of VCSEL mesa structures into a set of emitting VCSEL structures, for backside emission through the substrate, and a set of non-emitting VCSEL structures. The additional layer structure may include a first contact layer on the set of epitaxial layers at a base of the plurality of VCSEL mesa structures and surrounding each of the plurality of VCSEL mesa structures, and a second contact layer on top surfaces of the set of emitting VCSEL structures.

Abstract: In some implementations, a VCSEL device includes a substrate having a first surface and a second surface opposite the first surface. The VCSEL device may include a VCSEL array including a plurality of VCSELs disposed on the first surface of the substrate. The plurality of VCSELs may be configured for backside emission through the substrate. Respective emission areas for the plurality of VCSELs may be defined on the second surface of the substrate. The respective emission areas may define a perimeter of an emission region of the VCSEL device. The VCSEL device may include an anti-reflection (AR) coating on the second surface of the substrate. The VCSEL device may include a plurality of dummy posts disposed on the AR coating. The plurality of dummy posts may be positioned within the emission region, outside of the respective emission areas for the plurality of VCSELs.

Abstract: A package assembly includes a circuit substrate, a top-emitting (TE) vertical cavity surface emitting laser (VCSEL) die having a two-dimensional (2D) matrix addressable emitter array, and a driver integrated circuit (IC) having a flip-chip interconnect configuration. The TE-VCSEL die and the driver IC are coupled together to form a die stack that is mounted to the circuit substrate, with the TE-VCSEL die arranged between the driver IC and the circuit substrate. TE-VCSEL die comprises an optical output arranged at a main surface coupled to the driver IC. The optical output is configured to output light generated by one or more emitters of the emitter array. Thus, the TE-VCSEL die is configured to emit light away from the circuit substrate.

Abstract: An emitter includes a substrate; a current-blocking distributed Bragg reflector (DBR) arranged on the substrate, wherein the current-blocking DBR includes a plurality of p-n junctions connected vertically in series to form a bidirectional current-blocking structure; a bottom contact layer arranged on the current-blocking DBR; a bottom DBR arranged on the bottom contact layer; a top DBR arranged on the bottom DBR; an active region configured to generate a laser light, wherein the active region is arranged between the bottom DBR and the top DBR; a top contact layer arranged on the top DBR; and an optical output arranged over the top DBR, wherein the emitter is configured to emit the laser light via the optical output.

Abstract: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs. The emitter assembly may include a plurality of conductive pillars electrically connected to the VCSEL chip. The emitter assembly may include a dummy pillar, electrically isolated from the VCSEL chip, mating with a slot. The VCSEL chip may include one of the dummy pillar or the slot.

Abstract: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs respectively associated with a plurality of first electrical contacts. A first spacing of the plurality of first electrical contacts may define a first pitch. The emitter assembly may include a redistribution layer, disposed on the VCSEL chip, to increase the first pitch of the plurality of first electrical contacts. The emitter assembly may include a carrier having a plurality of second electrical contacts. A second spacing of the plurality of second electrical contacts may define a second pitch greater than the first pitch. The emitter assembly may include a plurality of conductive pillars that electrically connect the plurality of first electrical contacts and the plurality of second electrical contacts via the redistribution layer. The plurality of conductive pillars may be arranged according to the second spacing.

Abstract: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs. The emitter assembly may include a plurality of conductive pillars electrically connected to the VCSEL chip, and a conductive pillar, of the plurality of conductive pillars, may have a solder cap at an end of the conductive pillar. The emitter assembly may include a pin extending into the solder cap.

Abstract: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs in a bottom-emitting configuration, and multiple VCSELs, of the plurality of VCSELs, may be grouped in a cluster. The emitter assembly may include a carrier, and the VCSEL chip may be in a flip chip configuration with the carrier. The emitter assembly may include a conductive pillar electrically connected to the multiple VCSELs grouped in the cluster.

Abstract: In some implementations, a vertical cavity surface emitting laser (VCSEL) array may include a substrate. In some implementations, the VCSEL array may include a set of cathodes disposed on the substrate in a first direction, wherein a cathode, of the set of cathodes, is defined by a serpentine shape. In some implementations, the VCSEL array may include a set of anodes disposed on the substrate in a second direction, wherein an anode, of the set of anodes, is defined by the serpentine shape.

Abstract: A method of fabricating a three-dimensional neural probe includes the steps of: growing thermal oxide layer; depositing a layer of Au/Cr on the thermal oxide layer; patterning the layer of Au/Cr; depositing a layer of parylene C; etching the thermal oxide layer to release a plurality of islands; and folding the islands onto one another in stacked relation. The layer of Au/Cr is formed by an evaporation process, and the layer of parylene C is deposited to a thickness of approximately 8 ?m. DRIE is used to perform the etching, and HF is used to remove the thermal oxide. A spacer is disposed intermediate of two of the islands.