Patents by Inventor YueFei Ge

YueFei Ge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6965985
    Abstract: A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the bypass, and the data is separately transferred to the aligner along a data path.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: November 15, 2005
    Assignee: Sun Mirosystems, Inc.
    Inventors: David M. Pini, Yuefei Ge, Anup S. Tirumala
  • Patent number: 6865098
    Abstract: A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: March 8, 2005
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Michael Edwin Ichiriu, Masaru Shinohara, YueFei Ge, Lan Lee
  • Publication number: 20030101332
    Abstract: A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the bypass, and the data is separately transferred to the aligner along a data path.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 29, 2003
    Inventors: David M. Pini, Yuefei Ge, Anup S. Tirumala