Patents by Inventor Yuefeng Jin

Yuefeng Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160326722
    Abstract: An energy-saving control system of an excavator, including an engine, a main pump (1), a pilot handle, a pilot pressure pump (2), pilot control valves (4), a controller, a main control multi-way valve (3) and an execution mechanism. The main pump controls the execution mechanism via the main control multi-way valve (3). The oil paths connecting the main pump to the execution mechanism are provided with high pressure sensors (6) for transmitting signals to the controller. The main pump adjusts the flow rate thereof according to the pressure of a negative feedback oil path. The oil paths interconnecting the output end of the pilot handle with the main pump is provided with electromagnetic proportional reducing valves (7) and shuttle valves (8). A pilot oil path sequentially passes through the electromagnetic proportional reducing valves (7) and the shuttle valves (8) to control the flow rate of the main pump.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventors: XIANJUN LI, QU WANG, JIASHENG QIN, YUFENG YANG, SHUHUI FEI, YUNXIAN WANG, LIJING SHI, YU ZHAO, YUEFENG JIN, HONGDA PAN, YUANLU YIN, MING ZHANG, ZHENGHUA WANG
  • Patent number: 8180955
    Abstract: A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: May 15, 2012
    Assignee: Via Telecom, Inc.
    Inventors: Rong Li, Huaqiao Wang, Yuefeng Jin
  • Publication number: 20100287327
    Abstract: A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order.
    Type: Application
    Filed: February 15, 2010
    Publication date: November 11, 2010
    Applicant: VIA TELECOM, INC.
    Inventors: Rong Li, Huaqiao Wang, Yuefeng Jin
  • Publication number: 20100077135
    Abstract: A wear leveling method for a non-volatile memory is provided. The non-volatile memory includes a plurality of data blocks, each corresponding to a time value. The data blocks are arranged according to a sequence of the time values corresponding thereto. The arranged blocks form a key table. An erase operation is determined whether to be executed for the data blocks. When the erase operation is executed for the data blocks, the corresponding data block is erased according to a sequence of the time values of the data blocks in the key table.
    Type: Application
    Filed: July 9, 2009
    Publication date: March 25, 2010
    Applicant: VIA TELECOM, INC.
    Inventors: Rong Li, Yuefeng Jin, Li Wang