Abstract: A computing system including a water-resistant chassis, at least one electronic component with a heat sink, and a gap filler. The heat sink includes an arrangement of fins separated by inter-fin spaces. The gap filler is in contact with both the heat sink and the water-resistant chassis. The gap filler is positioned in the inter-fin spaces to provide a heat conduction path between the heat sink and the chassis.

Abstract: An asymmetric half-bridge converter is provided. The asymmetric half-bridge converter includes a switch circuit, a resonance tank, a current sensor, and a controller. The current sensor senses a waveform of a resonance current flowing through the resonance tank to generate a sensing result. The controller determines the sensing result. When the sensing result indicates that an ending current value of a primary resonance waveform of the resonance current is greater than a predetermined value, the controller performs a first switching operation on the switch circuit. When the sensing result indicates that the ending current value of the primary resonance waveform is less than or equal to the predetermined value, the controller performs a second switching operation on the switch circuit.

Abstract: An asymmetric half-bridge converter is provided. The asymmetric half-bridge converter includes a switch circuit, a resonance tank, a current sensor, and a controller. The current sensor senses a waveform of a resonance current flowing through the resonance tank to generate a sensing result. The controller determines the sensing result. When the sensing result indicates that an ending current value of a primary resonance waveform of the resonance current is greater than a predetermined value, the controller performs a first switching operation on the switch circuit. When the sensing result indicates that the ending current value of the primary resonance waveform is less than or equal to the predetermined value, the controller performs a second switching operation on the switch circuit.

Abstract: A pulse width modulation control circuit and a control method of a pulse width modulation signal are provided. A counter circuit generates a count value according to a phase-locked loop clock, and resets the count value according to a transition point of a synchronization signal. A comparison circuit compares the count value with a duty ratio set value, and sets the pulse width modulation signal to a high level while the count value is less than the duty ratio set value.

Abstract: A pulse width modulation control circuit and a control method of a pulse width modulation signal are provided. A counter circuit generates a count value according to a phase-locked loop clock, and resets the count value according to a transition point of a synchronization signal. A comparison circuit compares the count value with a duty ratio set value, and sets the pulse width modulation signal to a high level while the count value is less than the duty ratio set value.

Abstract: A charger calibrating device and a calibrating method thereof. The device comprises a control module and a processing module. The control module controls a charger to be calibrated to perform a first stage charging and a second stage charging on an electronic device. The processing module performs an adjusting process according to the second stage charging time for adjusting the high level period of the PWM signal in the charging circuit of the charger. In the adjusting process, generating an updated high level period by adding or decreasing a preset adjusting amplitude, and decrease the preset adjusting amplitude by half to generate an updated adjusting amplitude. The processing module terminates the calibrating process after repeating the aforementioned calibrating loop a preset number of times.

Abstract: A flash charging protection circuit and a control method thereof adapted to a charging circuit coupled to a power supply are provided. An analog-to-digital converter receives a feedback voltage output from the charging circuit and an input voltage output from the power supply. A power voltage detection module detects whether the input voltage is abnormal or not. A charging state detection module detects whether a rising curve of the feedback voltage is abnormal or not. If a controller receives a power abnormal signal or a charging state abnormal signal, the controller disables a pulse width modulation signal generator to produce a pulse width modulation signal.

Abstract: An apparatus for providing clock and a method thereof are provided. The provided apparatus includes a frequency generation unit and a control unit. The frequency generation unit decides amplitude of a clock signal to be a first amplitude or a second amplitude in response to a mode signal. The frequency generation unit converts an external oscillation signal into the clock signal. The control unit receives the clock signal, and outputs the mode signal in response to a system status signal. The control unit outputs the clock signal to external when determining that the clock signal has a stable oscillation. When the system status signal is a power on signal, the first amplitude is used as the amplitude of the clock signal, and when the system status signal is a power off signal, the second amplitude smaller than the first amplitude is used as the amplitude of the clock signal.

Abstract: A digital flash charger controller includes a transformer, a power supply element, and an application-specific integrated circuit (ASIC). A secondary side of the transformer is electrically connected to an energy storage device, and the power supply element is used to supply an electric power to a primary side of the transformer. The ASIC outputs a pulse-width-modulation (PWM) signal to control whether the electric power is input to the primary side, and the ASIC converts a sensing signal generated at the secondary side of the transformer to a digital signal, and tracks a sensing negative edge of the sensing signal according to the digital signal to adjust a cutoff time of the PWM signal, such that the next pulse positive edge approaches the corresponding sensing negative edge.

Abstract: A charger calibrating device and a calibrating method thereof. The device comprises a control module and a processing module. The control module controls a charger to be calibrated to perform a first stage charging and a second stage charging on an electronic device. The processing module performs an adjusting process according to the second stage charging time for adjusting the high level period of the PWM signal in the charging circuit of the charger. In the adjusting process, generating an updated high level period by adding or decreasing a preset adjusting amplitude, and decrease the preset adjusting amplitude by half to generate an updated adjusting amplitude. The processing module terminates the calibrating process after repeating the aforementioned calibrating loop a preset number of times.

Abstract: An apparatus for providing clock and a method thereof are provided. The provided apparatus includes a frequency generation unit and a control unit. The frequency generation unit decides amplitude of a clock signal to be a first amplitude or a second amplitude in response to a mode signal. The frequency generation unit converts an external oscillation signal into the clock signal. The control unit receives the clock signal, and outputs the mode signal in response to a system status signal. The control unit outputs the clock signal to external when determining that the clock signal has a stable oscillation. When the system status signal is a power on signal, the first amplitude is used as the amplitude of the clock signal, and when the system status signal is a power off signal, the second amplitude smaller than the first amplitude is used as the amplitude of the clock signal.

Abstract: A digital flash charger controller includes a transformer, a power supply element, and an application-specific integrated circuit (ASIC). A secondary side of the transformer is electrically connected to an energy storage device, and the power supply element is used to supply an electric power to a primary side of the transformer. The ASIC outputs a pulse-width-modulation (PWM) signal to control whether the electric power is input to the primary side, and the ASIC converts a sensing signal generated at the secondary side of the transformer to a digital signal, and tracks a sensing negative edge of the sensing signal according to the digital signal to adjust a cutoff time of the PWM signal, such that the next pulse positive edge approaches the corresponding sensing negative edge.

Abstract: The present invention comprises a burst mode controller (BMC) having a slot control block, a CPU, a single-port data memory, a DMA controller and a control signal selector. When the slot control block sends a logic high enable signal to the control signal selector celecting meane within a first predetermined time slot, the BMC is enabled to transmit/receive message-type data to/from the signal port data memory. When the slot control block sends a logic low enable signal to the control signal selector within a predetermined second time slot, the DMA is enabled to access message-type data stored in the single-port data memory to a peripheral device in accordance with commands provided by the CPU.

Abstract: An automatic gain controller and the controlling method thereof are disclosed. The automatic gain controller includes a first multiplexer for receiving an input signal and a gain and generating a first output, a second multiplexer for receiving a signal time constant and a gain time constant and generating a second output, a filter electrically connected to the first multiplexer and the second multiplexer for generating one of a signal-energy and an actual gain in response to the first output and the second output, a signal-energy processing device electrically connected to the filter, the first multiplexer and the second multiplexer for generating the gain and the gain time constant in response to the signal-energy, and a multiplier electrically connected to the filter for multiplying the actual gain by the input signal to generate an output signal.

Abstract: A half duplex device and signal processing method thereof. First, a signal detection unit of a signal detector of a half duplex device obtains a short-term power and long-term power. Next, a data update unit of the signal detector sets a short-term power threshold as a default threshold, determines whether the long-term power is greater than the default threshold, sets the short-term power threshold value equal to the long-term power value if the long-term power value is greater than the default threshold value, and provides smooth performance in a noisy environment.

Abstract: A device for processing a frequency shift keying (FSK) signal including caller ID information that comprises an analog-to-digital converter (ADC) converting the FSK signal into a digital FSK signal, the FSK signal further comprising a first frequency component, a second frequency component including the caller ID information, and a third frequency component, a first filter attenuating the first and third frequency components of the digital FSK signal to provide a first signal, a second filter attenuating the second frequency component of the digital FSK signal to provide a second signal, and a circuit calculating an energy level for each of the first and second signals, and selecting the first signal for output if the energy level of the first signal is smaller than that of the second signal, and selecting the digital FSK signal for output if the energy level of the first signal is greater than that of the second signal.

Abstract: A half duplex device and signal processing method thereof. First, a signal detection unit of a signal detector of a half duplex device obtains a short-term power and long-term power. Next, a data update unit of the signal detector sets a short-term power threshold as a default threshold, determines whether the long-term power is greater than the default threshold, sets the short-term power threshold value equal to the long-term power value if the long-term power value is greater than the default threshold value, and provides smooth performance in a noisy environment.

Abstract: A device for processing a frequency shift keying (FSK) signal including caller ID information that comprises an analog-to-digital converter (ADC) converting the FSK signal into a digital FSK signal, the FSK signal further comprising a first frequency component, a second frequency component including the caller ID information, and a third frequency component, a first filter attenuating the first and third frequency components of the digital FSK signal to provide a first signal, a second filter attenuating the second frequency component of the digital FSK signal to provide a second signal, and a circuit calculating an energy level for each of the first and second signals, and selecting the first signal for output if the energy level of the first signal is smaller than that of the second signal, and selecting the digital FSK signal for output if the energy level of the first signal is greater than that of the second signal.

Abstract: A adaptive deciding method and apparatus for frequency shift key signals are provided to sample the demodulated FSK signal, input the values of the sample points in sequence to a sample group, and compare at least a pair of the sample points, thereby finding out the central point of the FSK signal to improve decoding due to signal attenuation.

Abstract: An automatic gain controller and the controlling method thereof are disclosed. The automatic gain controller includes a first multiplexer for receiving an input signal and a gain and generating a first output, a second multiplexer for receiving a signal time constant and a gain time constant and generating a second output, a filter electrically connected to the first multiplexer and the second multiplexer for generating one of a signal-energy and an actual gain in response to the first output and the second output, a signal-energy processing device electrically connected to the filter, the first multiplexer and the second multiplexer for generating the gain and the gain time constant in response to the signal-energy, and a multiplier electrically connected to the filter for multiplying the actual gain by the input signal to generate an output signal.