Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: A pixel array substrate, including multiple pixel structures, is provided. Each of the pixel structures includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer, and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode within an opening of the color filter pattern.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: A display device has a display area and a peripheral area and includes data lines, scan lines, gate transmission lines, and sub-pixels. The data lines and the gate transmission lines extend from the peripheral area into the display area. The data lines located in the display area extend along a first direction. The scan lines are located in the display area and extend along a second direction intersecting the first direction. The gate transmission lines are electrically connected to the scan lines. One of the gate transmission lines includes first, second, and third wires located in the display area. The first and third wires extend along the first direction. The second wire extends along the second direction. The first, second and third wires are electrically connected in sequence. The third wire is electrically connected to one of the scan lines.

Abstract: A pixel array substrate, including multiple pixel structures, is provided. Each of the pixel structures includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer, and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode within an opening of the color filter pattern.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.

Abstract: A display device has a display area and a peripheral area and includes data lines, scan lines, gate transmission lines, and sub-pixels. The data lines and the gate transmission lines extend from the peripheral area into the display area. The data lines located in the display area extend along a first direction. The scan lines are located in the display area and extend along a second direction intersecting the first direction. The gate transmission lines are electrically connected to the scan lines. One of the gate transmission lines includes first, second, and third wires located in the display area. The first and third wires extend along the first direction. The second wire extends along the second direction. The first, second and third wires are electrically connected in sequence. The third wire is electrically connected to one of the scan lines.

Abstract: A multiple-style complex window of two uses includes a casing, a push-out window, a slide window and a screen fixed in said casing. The push-out window may be pushed out, and the slide window and the screen may be pushed sidewise to an inside or behind the push-out window. A middle post is provided to separate the push-out window from the slide window and the screen. The push-out window, the slide window and the screen are positioned orderly from the outside to the inside so that the latter two may be slid to behind the push-out window.