Abstract: A display device includes first and second pixel circuits, first and second gate lines, and first and second transmission lines. The first pixel circuit emits light according to a data signal, and is charged according to a first gate signal. The second pixel circuit emits light according to the data signal, and is charged according to a second gate signal. The first gate line is located between the first second pixel circuits, and provides the first gate signal. The second gate line provides the second gate signal. The first transmission line provides the second gate signal to the second gate line. The second transmission line is located between the first transmission line and the second pixel circuit, crosses over the second gate line, and provides the first gate signal to the first gate line.

Abstract: Apparatus and methods for tracking sub-micro-operations and groups thereof are described. An integrated circuit includes a load store unit configured to receive store micro-operations cracked from a vector store instruction. The load store unit is configured to unroll multiple store sub-micro-operations from each of the store micro-operations. The load store unit includes an issue status vector to track issuance of each sub-micro-operation, an unroll status vector to track unrolling of each sub-micro-operation associated with a group of sub-micro-operations, and a replay status vector to track a replayability of sub-micro-operations associated with the group of sub-micro-operations.

Abstract: Apparatus and methods for processing of a vector load or store micro-operation with mask information as a no-operation (no-op) when a mask vector for the vector load or store micro-operation has all inactive mask elements or processing vector load or store sub-micro-operation(s) with active mask element(s) are described. An integrated circuit includes a load store unit configured to receive load or store micro-operations cracked from a vector load or store operation, determine that a mask vector for the vector load or store micro-operation is fully inactive, and process the vector load or store micro-operation as a no-operation. If the mask vector is not fully inactive, the vector load or store micro-operation is unrolled into vector load or store sub-micro-operation(s) which have active mask element(s). Vector load or store sub-micro-operation(s) which have inactive mask element(s) are ignored.

Abstract: A display device includes first and second pixel circuits, first and second gate lines, and first and second transmission lines. The first pixel circuit emits light according to a data signal, and is charged according to a first gate signal. The second pixel circuit emits light according to the data signal, and is charged according to a second gate signal. The first gate line is located between the first second pixel circuits, and provides the first gate signal. The second gate line provides the second gate signal. The first transmission line provides the second gate signal to the second gate line. The second transmission line is located between the first transmission line and the second pixel circuit, crosses over the second gate line, and provides the first gate signal to the first gate line.

Abstract: A method for executing vector iota (viota) operation is disclosed. The method includes fetching a viota instruction, decoding the viota instruction into multiple viota micro-operations (uops), computing a first element viota value of a respective viota uop, determining a respective last element viota value of the respective viota uop based on the first element viota value of the respective uop, and writing the respective last element viota value of the respective viota uop to an allocated physical register. Each viota uop of the multiple viota uops has multiple elements, and each element has a viota value corresponding to a sum of active mask bits of preceding elements of the viota uops. The multiple elements of each viota uop comprise at least a first element that has a starting bit position of a respective uop and a last element that has an ending bit position of the respective uop.

Abstract: A method for tracking of data readiness for load and store operations is disclosed. The method includes establishing a Load Transfer Buffer (LTB) entry, initializing a write counter configured to track a number or progress of write data that are expected to update the LTB entry, and tracking the number or progress of the write data that are expected to update the LTB entry. The tracking can include setting, in the write counter, the number of the write data that are expected to update the LTB entry, maintaining, until a next respective write data arrives to the LTB entry a current value corresponding to a respective number of write data left to update the LTB entry, and after receiving the next respective write data, adjusting the write counter to reflect a respective number of write data left to update the LTB entry.

Abstract: Systems and methods are disclosed for accelerated vector-reduction operations. Some systems may include a vector register file configured to store register values of an instruction set architecture in physical registers; and an execution circuitry configured to, responsive to a folding micro-op: read a vector from a physical register of the vector register file or from bypass circuitry; partition the elements of the vector into a first subset of elements with even indices and a second subset with elements with odd indices; and apply a reduction operation to combine elements from the second subset of elements with corresponding elements from the first subset of elements to obtain a set of reduced elements.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: A pixel array substrate, including multiple pixel structures, is provided. Each of the pixel structures includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer, and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode within an opening of the color filter pattern.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: A display device has a display area and a peripheral area and includes data lines, scan lines, gate transmission lines, and sub-pixels. The data lines and the gate transmission lines extend from the peripheral area into the display area. The data lines located in the display area extend along a first direction. The scan lines are located in the display area and extend along a second direction intersecting the first direction. The gate transmission lines are electrically connected to the scan lines. One of the gate transmission lines includes first, second, and third wires located in the display area. The first and third wires extend along the first direction. The second wire extends along the second direction. The first, second and third wires are electrically connected in sequence. The third wire is electrically connected to one of the scan lines.

Abstract: A pixel array substrate, including multiple pixel structures, is provided. Each of the pixel structures includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer, and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode within an opening of the color filter pattern.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.

Abstract: A display device has a display area and a peripheral area and includes data lines, scan lines, gate transmission lines, and sub-pixels. The data lines and the gate transmission lines extend from the peripheral area into the display area. The data lines located in the display area extend along a first direction. The scan lines are located in the display area and extend along a second direction intersecting the first direction. The gate transmission lines are electrically connected to the scan lines. One of the gate transmission lines includes first, second, and third wires located in the display area. The first and third wires extend along the first direction. The second wire extends along the second direction. The first, second and third wires are electrically connected in sequence. The third wire is electrically connected to one of the scan lines.

Abstract: A multiple-style complex window of two uses includes a casing, a push-out window, a slide window and a screen fixed in said casing. The push-out window may be pushed out, and the slide window and the screen may be pushed sidewise to an inside or behind the push-out window. A middle post is provided to separate the push-out window from the slide window and the screen. The push-out window, the slide window and the screen are positioned orderly from the outside to the inside so that the latter two may be slid to behind the push-out window.