Abstract: An energy storage device fabrication method includes the steps of: mounting a frame shell at the top wall of a first plate electrode, mounting a glue frame at the top wall of the first plate electrode around the frame shell to have the top wall of the glue frame be disposed above the elevation of top wall of the frame shell, filling an electrolyte solution in the accommodation chamber defined by the glue frame, the frame shell and the top wall of the first plate member under a vacuum environment to form a first unit, mounting a second unit with a second plate electrode at the top wall of the glue frame, and bonding the second unit to the glue frame of the first unit under a vacuum environment to seal the electrolyte solution in between the first plate electrode and the second plate electrode.

Abstract: A thin-film solar cell and a method for manufacturing the same are presented, in which the dopant concentration turns low in a sloping way. The solar cell includes a substrate, a first contact region, a photoelectric conversion layer, and a second contact region. The first contact region a photoelectric conversion layer, and a second contact region are disposed on the substrate. At least one of the first contact region and the second contact region contains an N-type dopant, and the concentration of the N-type dopant is decreased gradually in a direction towards the photoelectric conversion layer. Through the thin-film solar cell and the method for manufacturing the same, the conversion efficiency of the solar cell is improved, and the thin-film solar cell and the manufacturing method are capable of being integrated with an existing manufacturing process of a solar cell, thereby simplifying the manufacturing process and reducing the cost.

Abstract: A first compensation factor, a second compensation factor and a third compensation factor are provided to improve a capacitance-voltage (C-V) method for measuring an effective channel length of a metal-oxide-semiconductor field effect transistor (MOSFET), and an overlap length of a gate and a source and a drain of the transistor. The first compensation factor is calculated by measuring two unit length gate capacitances of the transistor. The second compensation factor is calculated by measuring two unit length overlap capacitances of the transistor. The third compensation factor is a ratio of the second compensation factor to the first compensation factor.