Abstract: The disclosure provides a display apparatus and a data driving integrated circuit thereof for removing the interference patterns caused by radio wave interference. In the disclosure, a data driving integrated circuit includes a gamma voltage generating circuit, power terminals for receiving power voltages of the gamma voltage generating circuit. The data driving integrated circuit couples dummy terminals to the power terminals, so as to decrease the equivalent impedance of the power terminals through a parallel connection between the I/O ESD protection circuits. Therefore, the DC offset of the power voltages caused by the radio wave interference may be decreased.

Abstract: A source driver for a panel includes a plurality of driver cells. Each of the driver cells includes an output driver, a plurality of bias voltage generators and a selector. The output driver is configured to output a plurality of display data to the panel. The plurality of bias voltage generators is coupled to the output driver. Each of the bias voltage generators is configured to provide at least one bias voltage for the output driver. The selector, coupled to the output driver, is configured to select the bias voltage from one of the bias voltage generators to be provided for the output driver according to the plurality of display data.

Abstract: The disclosure provides a display apparatus and a data driving integrated circuit thereof for removing the interference patterns caused by radio wave interference. In the disclosure, a data driving integrated circuit includes a gamma voltage generating circuit, power terminals for receiving power voltages of the gamma voltage generating circuit. The data driving integrated circuit couples dummy terminals to the power terminals, so as to decrease the equivalent impedance of the power terminals through a parallel connection between the I/O ESD protection circuits. Therefore, the DC offset of the power voltages caused by the radio wave interference may be decreased.

Abstract: A source driver utilized for a display device and switching between two operational modes includes a reception module for receiving a plurality of display information and a plurality of transmission channels. Each transmission channel includes a register module for receiving one of the plurality of display information; a voltage level transformer for determining a voltage level of the one of display information; a polarization digital-to-analog converter for processing a digital-to-analog operation for the voltage level of the one display information; and an output module for outputting a plurality of voltage levels of the display information. The voltage levels of every two adjacent transmission channels include different polarization of voltage levels, and the output module processes an odd-number switching operation before outputting the plurality of voltage levels.

Abstract: A source driver utilized for a display device and switching between two operational modes includes a reception module for receiving a plurality of display information and a plurality of transmission channels. Each transmission channel includes a register module for receiving one of the plurality of display information; a voltage level transformer for determining a voltage level of the one of display information; a polarization digital-to-analog converter for processing a digital-to-analog operation for the voltage level of the one display information; and an output module for outputting a plurality of voltage levels of the display information. The voltage levels of every two adjacent transmission channels include different polarization of voltage levels, and the output module processes an odd-number switching operation before outputting the plurality of voltage levels.

Abstract: A driver architecture includes multiple drivers connected in series. An (i)th driver includes a reading circuit, a configuration circuit, a clock generator and a data input/output start pulse (DIO) generation circuit. The reading circuit reads an (i)th DIO outputted from an (i?1)th driver according to multiple reading pulses. The (i)th DIO includes an (i?1)th configuration of an (i?1)th driver and an (i)th trigger pulse. The (i)th trigger pulse is for activating the (i)th driver. The configuration circuit configures an (i)th configuration of the (i)th driver. The clock generator generates an (i+1)th trigger pulse for activating an (i+1)th driver. The DIO generation circuit outputs an (i+1)th DIO to the (i+1)th driver. The (i+1)th DIO includes the (i)th configuration and the (i+1)th trigger pulse.