Patents by Inventor Yueh-Ming Tung
Yueh-Ming Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11462485Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.Type: GrantFiled: March 23, 2021Date of Patent: October 4, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Ying-Chuan Li, Ping-Hua Chu
-
Patent number: 11462454Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.Type: GrantFiled: January 26, 2021Date of Patent: October 4, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
-
Publication number: 20220285217Abstract: The wafer thinning method of the present disclosure includes: providing a wafer having a front surface and a back surface opposite to the front surface; grinding the back surface of the wafer with a grinding bit to thin the wafer to a predetermined thickness; dicing the wafer with a dicing blade; ablating the wafer by performing a chemical solution or plasma process on the back surface of the wafer to thin the wafer; and separating the wafer into a plurality of dies.Type: ApplicationFiled: March 29, 2021Publication date: September 8, 2022Inventors: YUEH-MING TUNG, CHIA-MING YANG, GUAN-LIN PAN, JUNG-WEI CHEN, JIAN-DE LEU
-
Publication number: 20220270981Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.Type: ApplicationFiled: March 23, 2021Publication date: August 25, 2022Inventors: YUEH-MING TUNG, CHIA-MING YANG, JUNG-WEI CHEN, YING-CHUAN LI, PING-HUA CHU
-
Publication number: 20220199428Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.Type: ApplicationFiled: February 2, 2021Publication date: June 23, 2022Inventors: YUEH-MING TUNG, CHIA-MING YANG, JUNG-WEI CHEN, JIAN-DE LEU, GUAN-LIN PAN
-
Publication number: 20220189842Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.Type: ApplicationFiled: January 26, 2021Publication date: June 16, 2022Inventors: YUEH-MING TUNG, CHIA-MING YANG, JUNG-WEI CHEN, JIAN-DE LEU, GUAN-LIN PAN
-
Patent number: 11355356Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.Type: GrantFiled: February 2, 2021Date of Patent: June 7, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
-
Publication number: 20210005574Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a first substrate, a first die, a plurality of first electrical contacts, a first encapsulant, a second substrate, a second die, a third die, a plurality of second electrical contacts, a second encapsulant and an adhesive layer. The first die is disposed on a first surface of the first substrate. The first electrical contacts are disposed on a second surface of the first substrate and are electrically connected to the first die. The first encapsulant is formed on the first surface of the first substrate to enclose the first die. The second and third dies are disposed on a first surface of the second substrate. The second electrical contacts are disposed on a second surface of the second substrate and are electrically connected to the second and third dies. The second encapsulant is formed on the first surface of the second substrate to enclose the second and third dies.Type: ApplicationFiled: March 11, 2020Publication date: January 7, 2021Inventors: YUEH-MING TUNG, CHIA-MING YANG, HUI-YEN TSAI, YU-CHEN LIN, PEI-JUNG SU
-
Publication number: 20120038839Abstract: A micro projector module according to the present invention is provided. The micro projector module includes a substrate, a controller chip, a LCOS chip, a glass and a liquid crystal layer. The controller chip is positioned on the upper surface of the substrate and electrically connected to the substrate. The LCOS chip is positioned on the controller chip and electrically connected to the substrate. The glass is positioned on the LCOS chip and the liquid crystal layer is disposed between the LCOS chip and glass.Type: ApplicationFiled: October 7, 2010Publication date: February 16, 2012Applicant: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh Ming TUNG, Chia Ming YANG, Shu Hui LIN, Yuan Wei LIU, Wei Fang LIN
-
Patent number: 7948772Abstract: A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board.Type: GrantFiled: February 16, 2009Date of Patent: May 24, 2011Assignee: Orient Semiconductor ElectronicsInventors: Yueh-Ming Tung, Kuo-Yang Sun, Chia-Ming Yang, Chung-Lun Lee, Jin-Chun Wen, Yuan-Wei Liu, Wei-Mao Hung
-
Publication number: 20090253230Abstract: A method for manufacturing a stack chip package structure is disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire.Type: ApplicationFiled: June 17, 2009Publication date: October 8, 2009Inventors: Yueh-Ming TUNG, Chia-Ming Yang, Shu-Hui Lin, Ta-Fa Lin, Mien-Fang Sung
-
Publication number: 20090189295Abstract: A stack chip package structure and a manufacturing method thereof are disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire.Type: ApplicationFiled: May 13, 2008Publication date: July 30, 2009Inventors: Yueh-Ming TUNG, Chia-Ming Yang, Shu-Hui Lin, Ta-Fa Lin, Mien-Fang Sung
-
Publication number: 20090154040Abstract: A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board.Type: ApplicationFiled: February 16, 2009Publication date: June 18, 2009Applicant: ORIENT SEMICONDUCTOR ELECTRONICSInventors: Yueh-Ming Tung, Kuo-Yang Sun, Chia-Ming Yang, Chung-Lun Lee, Jin-Chun Wen, Yuan-Wei Liu, Wei-Mao Hung
-
Publication number: 20080113472Abstract: A film includes a removable base material, a resin layer and a plurality of arc elastomers. The resin layer is a partially-cured resin which is in a half-melting state with viscosity at a temperature higher than a first temperature and in a solid state without viscosity at a temperature lower than a second temperature, and the resin layer in a solid state is adhered on the base material. The arc elastomers are disposed inside the resin layer. The present invention further provides a chip packaging process using the film.Type: ApplicationFiled: November 8, 2007Publication date: May 15, 2008Inventors: Yueh Ming Tung, Kuo Yang Sun, Chia Ming Yang, Hung Tai Mai, Hui Chi Liu
-
Publication number: 20080007932Abstract: A memory card with electrostatic discharge (ESD) protection is provided. The memory card includes a board, a set of contacts, at least one chip and an ESD protection path. The board having a signal path not electrically connected to the edge of the board. The ESD protection path for transmitting ESD current is disposed on the board. Furthermore, a part of the ESD protection path extends to the edge of the board.Type: ApplicationFiled: September 12, 2006Publication date: January 10, 2008Applicant: ORIENT SEMICONDUCTOR ELECTRONICSInventors: Yueh-Ming Tung, Kuo-Yang Sun, Chia-Ming Yang, Chung-Lun Lee, Jin-Chun Wen, Yuan-Wei Liu, Wei-Mao Hung
-
Publication number: 20070205493Abstract: A semiconductor package structure is disclosed. The structure includes a lead frame, a semiconductor chip, a plurality of metallic conducting wires, an encapsulation, a barrier layer and a pure tin layer, herein the lead frame has at least one die pad, a plurality of inner leads and outer leads. The semiconductor chip is disposed on the die pad. The metallic conducting wires electrically connect the semiconductor chip and the inner leads. The encapsulation packages of the semiconductor chip, the die pad, the metallic conducting wires and the inner leads. The barrier layer covers each of the outer leads to prevent an inter-metallic compound produced by the outer leads and pure tin. The pure tin layer covers the barrier layer to increase the solder wettability for the outer leads. Besides, a method for manufacturing the semiconductor package structure is disclosed.Type: ApplicationFiled: June 12, 2006Publication date: September 6, 2007Inventors: Yueh-Ming Tung, Kuo-Yang Sun, Chia-Ming Yang, Hung-Tai Mai, Hui-Ying Hsu
-
Patent number: D647096Type: GrantFiled: November 8, 2010Date of Patent: October 18, 2011Assignee: Orient Semiconductor Electronics, LimitedInventors: Yueh Ming Tung, Chia Ming Yang, Hsiu Fang Tsai, Shu Hui Lin, Hung Lin Chiang
-
Patent number: D647097Type: GrantFiled: November 12, 2010Date of Patent: October 18, 2011Assignee: Orient Semiconductor Electronics, LimitedInventors: Yueh Ming Tung, Chia Ming Yang, Hsiu Fang Tsai, Shu Hui Lin, Hung Lin Chiang