Abstract: A vertical alignment liquid crystal display device (VA-LCD) includes a display panel. The display panel includes a plurality of pixels. Each pixel unit includes a first thin film transistor (TFT), a second TFT, and a liquid crystal capacitor having a pixel electrode and a common electrode. The common electrode is applied with a common voltage, a first gray voltage is applied to the pixel electrode through a first TFT, and a second gray voltage is applied to the pixel electrode through a second TFT different from the first gray voltage, such that liquid crystal capacitor maintains two different gray voltages in a display frame time of the VA-LCD.

Abstract: A vertical alignment liquid crystal display device (VA-LCD) includes a display panel. The display panel includes a plurality of pixels. Each pixel unit includes a first thin film transistor (TFT), a second TFT, and a liquid crystal capacitor having a pixel electrode and a common electrode. The common electrode is applied with a common voltage, a first gray voltage is applied to the pixel electrode through a first TFT, and a second gray voltage is applied to the pixel electrode through a second TFT different from the first gray voltage, such that liquid crystal capacitor maintains two different gray voltages in a display frame time of the VA-LCD.

Abstract: A vertical alignment liquid crystal display device (VA-LCD) includes a display panel. The display panel includes a plurality of pixels. Each pixel unit includes a first thin film transistor (TFT), a second TFT, and a liquid crystal capacitor having a pixel electrode and a common electrode. The common electrode is applied with a common voltage, a first gray voltage is applied to the pixel electrode through a first TFT, and a second gray voltage is applied to the pixel electrode through a second TFT different from the first gray voltage, such that liquid crystal capacitor maintains two different gray voltages in a display frame time of the VA-LCD.

Abstract: A vertical alignment liquid crystal display device (VA-LCD) includes a display panel. The display panel includes a plurality of pixels. Each pixel unit includes a first thin film transistor (TFT), a second TFT, and a liquid crystal capacitor having a pixel electrode and a common electrode. The common electrode is applied with a common voltage, a first gray voltage is applied to the pixel electrode through a first TFT, and a second gray voltage is applied to the pixel electrode through a second TFT different from the first gray voltage, such that liquid crystal capacitor maintains two different gray voltages in a display frame time of the VA-LCD.

Abstract: A vertical alignment liquid crystal display device (VA-LCD) includes a display panel. The display panel includes a plurality of pixels. Each pixel unit includes a first thin film transistor (TFT), a second TFT, and a liquid crystal capacitor having a pixel electrode and a common electrode. The common electrode is applied with a common voltage, a first gray voltage is applied to the pixel electrode through a first TFT, and a second gray voltage is applied to the pixel electrode through a second TFT different from the first gray voltage, such that liquid crystal capacitor maintains two different gray voltages in a display frame time of the VA-LCD.

Abstract: A vertical alignment liquid crystal display device (VA-LCD) includes a display panel. The display panel includes a plurality of pixels. Each pixel unit includes a first thin film transistor (TFT), a second TFT, and a liquid crystal capacitor having a pixel electrode and a common electrode. The common electrode is applied with a common voltage, a first gray voltage is applied to the pixel electrode through a first TFT, and a second gray voltage is applied to the pixel electrode through a second TFT different from the first gray voltage, such that liquid crystal capacitor maintains two different gray voltages in a display frame time of the VA-LCD.

Abstract: A vertical alignment liquid crystal display device (VA-LCD) includes a display panel. The display panel includes a plurality of pixels. Each pixel unit includes a first thin film transistor (TFT), a second TFT, and a liquid crystal capacitor having a pixel electrode and a common electrode. The common electrode is applied with a common voltage, a first gray voltage is applied to the pixel electrode through a first TFT, and a second gray voltage is applied to the pixel electrode through a second TFT different from the first gray voltage, such that the liquid crystal capacitor maintains two different gray voltages in a display frame time of the VA-LCD.

Abstract: A pixel structure including a substrate, a scan line, a data line, a first and a second switching device, a first and a second pixel electrode, a first and a second bended pixel electrode, a first and a second connecting conductive layer, and a first and a second common line is provided. The scan line and data line demarcate a first and a second areas on the substrate, and the scan line is located between the two areas. The first and second switching devices are electrically connected to the scan line and the data line and are also electrically connected to the first and second pixel electrodes on the first and second areas respectively. The first and second bended pixel electrodes on the second and first areas are electrically connected to the first and second pixel electrodes through the first and second connecting conductive layers on the scan line respectively.

Abstract: A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.

Abstract: A liquid crystal display structure includes a top substrate, a bottom substrate, a gate metal layer, a pixel region, a main spacer, an auxiliary spacer and liquid crystal molecules. The gate metal layer and the pixel region are located between the top substrate and the bottom substrate, and are disposed on the bottom substrate. The bottom substrate overlaps with the gate metal layer. The pixel regions are adjacent to the gate layer metal but are separated from the gate metal layer. The main spacer and the auxiliary spacer are disposed on the top substrate. The main spacer extends downward to the gate metal layer, and the auxiliary spacer is located on the outside of the region which encompasses the gate metal layer, and does not overlap with the gate metal layer. The liquid crystal molecules are filled into the gap between the top substrate and the bottom substrate.

Abstract: A pixel circuit for a liquid crystal display panel includes a capacitor unit, a voltage-regulating mechanism, a first switching member, and a second switching member. The liquid crystal display panel includes a plurality of scan lines and data lines. The voltage-regulating mechanism is coupled to the first and second liquid crystal capacitors thereby enabling the first and second liquid crystal capacitors to be configured with different voltages when a voltage is applied to the capacitor unit. The first switching member is coupled to the capacitor unit, one of two corresponding scan lines, and one of two corresponding data lines. The second switching member is coupled to the second liquid crystal capacitor, the other of two corresponding scan lines.

Abstract: A pixel structure suitable for being disposed on a substrate is provided. The pixel structure includes a scan line, a data line, a thin film transistor (TFT), a primary pixel electrode, and at least one secondary pixel electrode. The scan line and the data line are disposed on the substrate. The TFT is disposed on the substrate and is electrically connected to the scan line and the data line. The primary pixel electrode is electrically connected to a drain electrode of the TFT through a contact hole. The secondary pixel electrode is disposed above the drain electrode and the drain electrode is electrically coupled to the secondary pixel electrode. Besides, a liquid crystal display (LCD) panel having the pixel structure is also provided.

Abstract: A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.

Abstract: A pixel structure includes a gate, a source, a first drain, a second drain, a third drain, a first pixel electrode, a second pixel electrode, a scan line and a data line. The gate, the source and the first drain form a first thin film transistor. The gate, the source and the second drain form a second thin film transistor. The gate, the second drain and the third drain form a sub-thin film transistor (sub-TFT). Additionally, the first pixel electrode is electrically connected to the first drain, and the second drain extends to a portion between the second pixel electrode and the substrate such that a capacitor-coupling electrode is formed. Moreover, the second pixel electrode is electrically connected to the third drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.

Abstract: A pixel structure including a scan line, a data line, a first sub-pixel, a coupling electrode and a second sub-pixel is provided. The first sub-pixel includes a first thin film transistor (TFT) and a first pixel electrode, and the first pixel electrode is electrically connected to the scan line and the data line via the first TFT. The coupling electrode is disposed above the data line and electrically insulated from the data line. The second sub-pixel includes a second thin film transistor and a second pixel electrode. The second pixel electrode is electrically connected to the second TFT, and the second TFT is electrically connected to the coupling electrode. When seeing an image from a slant direction, color shift of image can be solved by utilizing the pixel structure. Besides, a liquid crystal display panel having the described pixel structure is also provided.

Abstract: A vertical alignment liquid crystal display device (VA-LCD) includes a display panel. The display panel includes a plurality of pixels. Each pixel unit includes a liquid crystal capacitor. The liquid crystal capacitor maintains two different gray voltages in a display frame time of the VA-LCD.

Abstract: A pixel circuit for a liquid crystal display panel includes a capacitor unit, a voltage-regulating mechanism, a first switching member, and a second switching member. The liquid crystal display panel includes a plurality of scan lines and data lines. The voltage-regulating mechanism is coupled to the first and second liquid crystal capacitors thereby enabling the first and second liquid crystal capacitors to be configured with different voltages when a voltage is applied to the capacitor unit. The first switching member is coupled to the capacitor unit, one of two corresponding scan lines, and one of two corresponding data lines. The second switching member is coupled to the second liquid crystal capacitor, the other of two corresponding scan lines.

Abstract: A pixel structure suitable for being controlled by a scan line and a data line disposed on a thin film transistor (TFT) array substrate of a multi-domain vertical alignment (MVA) liquid crystal display is disclosed. The pixel structure includes a first TFT, a second TFT, a first pixel electrode, a second pixel electrode and a plurality of alignment members, wherein the first TFT and the second TFT are both electrically connected to the scan line and the data line. The first TFT has a first drain and the first pixel electrode is electrically connected to the first drain. The second TFT has a second drain and the second pixel electrode is floated over the second drain to form a coupling capacitor, while a voltage difference is established between the second pixel electrode and the first pixel electrode. The alignment members are disposed on the first and the second pixel electrode.

Abstract: A pixel structure including a substrate, a scan line, a data line, a first and a second switching device, a first and a second pixel electrode, a first and a second bended pixel electrode, a first and a second connecting conductive layer, and a first and a second common line is provided. The scan line and data line demarcate a first and a second areas on the substrate, and the scan line is located between the two areas. The first and second switching devices are electrically connected to the scan line and the data line and are also electrically connected to the first and second pixel electrodes on the first and second areas respectively. The first and second bended pixel electrodes on the second and first areas are electrically connected to the first and second pixel electrodes through the first and second connecting conductive layers on the scan line respectively.

Abstract: A pixel structure includes a gate, a source, a first drain, a second drain, a third drain, a first pixel electrode, a second pixel electrode, a scan line and a data line. The gate, the source and the first drain form a first thin film transistor. The gate, the source and the second drain form a second thin film transistor. The gate, the second drain and the third drain form a sub-thin film transistor (sub-TFT). Additionally, the first pixel electrode is electrically connected to the first drain, and the second drain extends to a portion between the second pixel electrode and the substrate such that a capacitor-coupling electrode is formed. Moreover, the second pixel electrode is electrically connected to the third drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source.