Patents by Inventor Yueh-Pu Kuo

Yueh-Pu Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529426
    Abstract: A data writing method, a valid data identifying method and a memory storage apparatus using the same are provided. The method includes receiving first data; using a first programming mode to write first sub-data of the first data into a first physical programmed unit of at least a first memory sub-module of a plurality of memory sub-modules, wherein a size of each of the first sub-data is the same as a preset size; and using a second programming mode to write remaining sub-data of the first data into a second physical programmed unit of a second memory sub-module of the plurality of memory submodules, wherein the size of the remaining sub-data is less than the preset size, and the second memory sub-module is different from a third memory sub-module of the first memory submodules which is a last memory sub-module for writing the first sub-data.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 7, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Sung-Yao Lin, Yueh-Pu Kuo, Yu-Min Hsiao
  • Publication number: 20190198115
    Abstract: A data writing method, a valid data identifying method and a memory storage apparatus using the same are provided. The method includes receiving first data; using a first programming mode to write first sub-data of the first data into a first physical programmed unit of at least a first memory sub-module of a plurality of memory sub-modules, wherein a size of each of the first sub-data is the same as a preset size; and using a second programming mode to write remaining sub-data of the first data into a second physical programmed unit of a second memory sub-module of the plurality of memory submodules, wherein the size of the remaining sub-data is less than the preset size, and the second memory sub-module is different from a third memory sub-module of the first memory submodules which is a last memory sub-module for writing the first sub-data.
    Type: Application
    Filed: March 2, 2018
    Publication date: June 27, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Sung-Yao Lin, Yueh-Pu Kuo, Yu-Min Hsiao