Abstract: For negative gate erase and programming of non-volatile floating gate EEPROM devices, large positive or negative voltages from one single negative charge pump and from one single positive charge pump are selectively switched onto a one or more memory sectors of twin-well CMOS negative-gate-erase memory cells. The control gate is negative during erasing and positive during programming. In order for FLASH memories to have minimum layout area, small sectors or arrays of EEPROM cells can be erased all at once using a charge pump which includes two pump capacitors to provide negative voltages to the gate terminals of one or more series PMOS transistors.

Abstract: An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

Abstract: A method of making an EEPROM cell structure which includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

Abstract: A flash EPROM memory array which operates at lower voltage power supply with no disturbance during operation. The memory circuit comprises a plurality of memory elements in a matrix fashion with each element including a semiconductor substrate, a drain region, a source region, a floating gate, a control gate, and a select gate. The low voltage power supply operation capability is achieved by a special arrangement on the said memory array such that the programming of the memory cell is achieved by high efficient hot electron injection which allows lower drain voltage during programming. No disturbance during program and erase occurs due to a control gate line running in parallel with the drain line. No disturbance access during read operation because of alternating drain and source lines such that the memory device can be read from the source side.

Abstract: An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

Abstract: Defects in the metal step coverage of a thin film semiconductor device are removed by annealing the metal layer with a pulsed electron beam.