Patents by Inventor Yueh Yale Ma
Yueh Yale Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9058289Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that use error control codes to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition.Type: GrantFiled: August 31, 2012Date of Patent: June 16, 2015Assignee: SANDISK ENTERPRISE IP LLCInventors: Ying Yu Tai, Yueh Yale Ma
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Patent number: 8938658Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.Type: GrantFiled: August 31, 2012Date of Patent: January 20, 2015Assignee: Sandisk Enterprise IP LLCInventors: Ying Yu Tai, Yueh Yale Ma
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Patent number: 8793543Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.Type: GrantFiled: August 31, 2012Date of Patent: July 29, 2014Assignee: Sandisk Enterprise IP LLCInventors: Ying Yu Tai, Yueh Yale Ma
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Publication number: 20130117640Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.Type: ApplicationFiled: August 31, 2012Publication date: May 9, 2013Inventors: YING YU TAI, YUEH YALE MA
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Publication number: 20130117613Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.Type: ApplicationFiled: August 31, 2012Publication date: May 9, 2013Inventors: Ying Yu Tai, Yueh Yale Ma
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Publication number: 20130117616Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.Type: ApplicationFiled: August 31, 2012Publication date: May 9, 2013Inventors: YING YU TAI, YUEH YALE MA
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Patent number: 6798012Abstract: A four-terminal dual-bit double-polysilicon source-side injection flash EEPROM cell, capable of storing two bits of information includes a right junction (which can serve as a cell drain or a source), a left junction (which can serve as a cell source or drain), a select-gate, and two floating gates. The two floating gates are insulated from the select-gate by an inter-gate dielectric. The inter-gate dielectric has a “weak region” so that during erase-mode electrons can tunnel from the floating gate to the select-gate. The two bits in the cell are to be separately read or programmed, but are to be erased simultaneously. Programming of each bit is achieved through hot-carrier injection, while simultaneous erase of the two bits is achieved through electron-tunneling.Type: GrantFiled: December 10, 1999Date of Patent: September 28, 2004Inventors: Yueh Yale Ma, Chan-Sui Pang
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Patent number: 6714454Abstract: A four-terminal dual-bit double polysilicon source-side injection flash EEPROM cell, capable of storing two bits of information includes a right junction (which can serve as a cell drain or a source), a left junction (which can serve as a cell source or drain), a select-gate, and two floating gates. The two floating gates are insulated from the select-gate by an inter gate dielectric. The inter-gate dielectric has a “weak region” so that during erase mode electrons can tunnel from the floating gate to the select-gate. The two bits in the cell are to be separately read or programmed, but are to be erased simultaneously. Programming of each bit is achieved through hot-carrier injection, while simultaneous erase of the two bits is achieved through electron tunneling.Type: GrantFiled: October 24, 2002Date of Patent: March 30, 2004Inventors: Yueh Yale Ma, Chan-Sui Pang
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Patent number: 6699753Abstract: A method of fabricating a contact-less array of non-volatile memory cells includes: (A) forming over the substrate three stacks S1, S2 and S3 of first and second polysilicon layers; (B) forming in the substrate a drain region between the stacks S1 and S2, self-aligned to the edges of stacks S1 and S2, (C) forming side-wall spacers adjacent to edges of each polysilicon stack, (D) forming in the substrate a source region between stacks S2 and S3, self-aligned to the side-wall spacers; (E) forming a composite layer of HTO-Nitride-Polysilicon (ONP) over the array of memory cells immediately after step (B); (F) converting the ONP composite layer to ONO composite layer after step (D); (G) anisotropically etching the ONO composite layer to form ONO side-wall spacers adjacent to edges of the polysilicon stacks; and (H) growing select gate oxide over the row of polysilicon.Type: GrantFiled: July 16, 2002Date of Patent: March 2, 2004Assignee: Winbond Electronics CorporationInventors: Yueh Yale Ma, Takahiro Fukumoto
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Publication number: 20030071301Abstract: The present invention provides a novel erase method and apparatus for flash memory cells, with special emphasis on source-side injection cells, which enhances the erase efficiency of the cell. By activating the select-gate terminal of the cell using a negative voltage, it has been found for the first time that the erase performance can be improved. In one preferred embodiment, the present invention provides for three overlapping voltage signals applied to the cell terminals, of which two are negative and one positive. In another preferred embodiment, the memory cell is built on an “internal P-well” within an isolating N-well on the P-type substrate. In this case, by shifting the memory cell's body potential, the erase-mode uses four overlapping erase signals, two of which are negative, and two positive. With experimental data, it is demonstrated that better “magnitude balance” has been achieved for the highest erase voltages of opposite polarities.Type: ApplicationFiled: November 14, 2002Publication date: April 17, 2003Applicant: Winbond Electronics CorporationInventors: Keith R. Wald, Chan-Sui Pang, Yueh Yale Ma
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Publication number: 20030057474Abstract: A four-terminal dual-bit double polysilicon source-side injection flash EEPROM cell, capable of storing two bits of information includes a right junction (which can serve as a cell drain or a source), a left junction (which can serve as a cell source or drain), a select-gate, and two floating gates. The two floating gates are insulated from the select-gate by an inter gate dielectric. The inter-gate dielectric has a “weak region” so that during erase mode electrons can tunnel from the floating gate to the select-gate. The two bits in the cell are to be separately read or programmed, but are to be erased simultaneously. Programming of each bit is achieved through hot-carrier injection, while simultaneous erase of the two bits is achieved through electron tunneling.Type: ApplicationFiled: October 24, 2002Publication date: March 27, 2003Inventors: Yueh Yale Ma, Chan-Sui Pang
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Patent number: 6493262Abstract: The present invention is directed at a new nonvolatile memory cell structure, and a new erase method and apparatus for operating this and other nonvolatile memory cells, with special emphasis on source-side injection flash EEPROM cells, which enhances the erase efficiency of the cell. By activating the select-gate terminal of the cell using a negative voltage, it has been found for the first time that the erase performance can be improved. In one preferred embodiment, the present invention provides for three overlapping voltage signals applied to the cell terminals, of which two are negative and one positive. In another preferred embodiment, the memory cell is built on an “internal P-well” within an isolating N-well on the P-type substrate. In this case, by shifting the memory cell's body potential, the erase-mode uses four overlapping erase signals, two of which are negative, and two positive.Type: GrantFiled: May 31, 2000Date of Patent: December 10, 2002Assignee: Winbond Electronics CorporationInventors: Keith R. Wald, Chan-Sui Pang, Yueh Yale Ma
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Publication number: 20020182809Abstract: A contact-less array of self-aligned, triple polysilicon, source side injection, nonvolatile memory cells with metal-overlaid wordlines includes: a plurality of pairs of stacks of first, second and third layer polysilicon arrange in rows; a drain region between the two stacks in each pair of polysilicon stacks, the drain regions being self-aligned to the edges of the two stacks; and a source region between each of the two adjacent pairs of polysilicon stacks, the source regions being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks such that each source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located.Type: ApplicationFiled: July 16, 2002Publication date: December 5, 2002Applicant: Winbond Electronics CorporationInventors: Yueh Yale Ma, Takahiro Fukumoto
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Patent number: 6346725Abstract: A contact-less array of self-aligned, triple polysilicon, source side injection, nonvolatile memory cells with metal-overlaid wordlines includes: a plurality of pairs of stacks of first, second and third layer polysilicon arrange in rows; a drain region between the two stacks in each pair of polysilicon stacks, the drain regions being self-aligned to the edges of the two stacks; and a source region between each of the two adjacent pairs of polysilicon stacks, the source regions being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks such that each source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located.Type: GrantFiled: May 22, 1998Date of Patent: February 12, 2002Assignee: Winbond Electronics CorporationInventors: Yueh Yale Ma, Takahiro Fukumoto
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Publication number: 20010021563Abstract: A contact-less array of self-aligned, triple polysilicon, source side injection, nonvolatile memory cells with metal-overlaid wordlines includes: a plurality of pairs of stacks of first, second and third layer polysilicon arrange in rows; a drain region between the two stacks in each pair of polysilicon stacks, the drain regions being self-aligned to the edges of the two stacks; and a source region between each of the two adjacent pairs of polysilicon stacks, the source regions being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks such that each source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located.Type: ApplicationFiled: February 16, 2001Publication date: September 13, 2001Inventors: Yueh Yale Ma, Takahiro Fukumoto
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Patent number: 6211548Abstract: In producing a metal-gate non-volatile memory cell, a layer of oxide is formed over a silicon substrate. A floating gate is then formed over the oxide. Source and drain regions are then formed in the silicon substrate such that at least one of the edges of the floating gate is aligned with its corresponding edge of one of the source and drain regions. A high temperature anneal cycle is then carried out to remove the defects in the source and drain regions. A composite layer of either Oxide-Nitride-Oxide-Polysilicon (ONOP) coupling dielectric or Oxide-Polysilicon (OP) coupling dielectric is then formed over the floating gate. Finally, a control gate made from metal is formed over the composite layer of ONOP or OP coupling dielectric.Type: GrantFiled: April 17, 1998Date of Patent: April 3, 2001Inventor: Yueh Yale Ma
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Patent number: 5986941Abstract: A flash memory EEPROM device with a programming current limiting ability operates with six terminals and includes a source-side injection cell and a current limiter in series with the cell at a source region of the cell. During programming, an upper current limit is established for the overall channel current through the cell by controlling the voltage on a serial-gate of the current limiter. A second embodiment of a flash memory EEPROM device is structured with only four operating terminals, and includes a current limiting transistor integrally merged with a source-side injection cell. Merger is accomplished by eliminating the source junction of the injection cell and by combining the select-gate of the injection cell with the serial-gate of the current limiting transistor to create a conjoint select-gate. The unified channel under the conjoint select-gate consists of two channel sub-sections with different threshold adjustment implants and thus different threshold voltages.Type: GrantFiled: October 9, 1997Date of Patent: November 16, 1999Assignee: Bright Microelectronics, Inc.Inventors: Chan-Sui Pang, Yueh Yale Ma
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Patent number: 5768186Abstract: A high density single-poly metal-gate non-volatile memory cell uses a layer of tunnel oxide formed over a silicon substrate. A floating gate is formed over the tunnel oxide. Source and drain regions are ion implanted in the silicon substrate such that the source and drain regions are self-aligned to the corresponding edges of the floating gate. Following a high temperature anneal cycle which removes the defects in the source and drain regions, a composite layer of ONOP (Oxide-Nitride-Oxide-Polysilicon) coupling dielectric is formed over the floating gate. A metal, typically an aluminum alloy, forms the control gate of the memory cell on top of the composite layer of ONOP coupling dielectric.Type: GrantFiled: October 25, 1996Date of Patent: June 16, 1998Inventor: Yueh Yale Ma