Abstract: A controlled device includes a non-volatile memory, a power pin, and a controller. The controller is configured for performing, through a negotiation module, a power negotiation operation with a controlling device via the power pin; receiving a programming declaration from the controlling device via the power pin; disabling the negotiation module according to the programming declaration; receiving a programming data from the controlling device via the power pin after the negotiation module is disabled; and writing the programming data into the non-volatile memory. In other embodiment, the controlled device can further includes at least one configuration channel pin for receiving the programming declaration therethrough.

Abstract: An output input (I/O) control apparatus and a control method thereof are provided. The I/O control apparatus includes an interface control unit, a read-only memory, a random access memory, a multiplexer and a micro-process unit. The interface control unit is coupled to a memory apparatus through a bus, and the memory apparatus is external to the I/O control apparatus. The read-only memory stores judgment codes. The multiplexer is controlled by the micro-process unit to switch to the interface control unit, the read-only memory or the random access memory. When the bus is not busy, the micro-process unit can read data from the memory apparatus. When the bus is occupied and busy, the micro-process unit can read and execute codes from the read-only memory or the random access memory so as to avoid computer system instability or thermal damage.

Abstract: A super input/output (I/O) module for controlling a universal serial bus (USB) port of a computer system is provided. The super I/O module includes a USB host, a switch and a processor. The switch selectively couples the USB port of the computer system to the USB host or a controller of the computer system according to a switching signal. When a trigger event occurs, the processor provides the switching signal to control the switch, so as to couple the USB port of the computer system to the USB host and to transmit a basic input/output system (BIOS) code to a flash memory of the computer system via the switch and the USB port.

Abstract: A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal.

Abstract: An embodiment of the invention provides a clock calibration method to calibrate an internal clock signal of a computer. The method comprises: receiving an external clock signal from an external clock source; generating a pulse signal with a first duration according to the external clock signal; counting the internal clock signal according to the pulse signal to get a first count value; and calibrating the internal clock according to the first count value.

Abstract: A super I/O module for controlling at least one I/O port of a computer system is provided. The super I/O module includes a controller, a signal detector and a selector. The controller supports functions corresponding to the I/O port. The signal detector receives an input signal from the I/O port, and detects whether the input signal has an identification code. When detecting that the input signal has the identification code, the signal detector generates a selection signal according to the identification code. The selector receives the selection signal and selectively provides the input signal to the controller or a function circuit of the computer system according to the selection signal.

Abstract: An output input (I/O) control apparatus and a control method thereof are provided. The I/O control apparatus includes an interface control unit, a read-only memory, a random access memory, a multiplexer and a micro-process unit. The interface control unit is coupled to a memory apparatus through a bus, and the memory apparatus is external to the I/O control apparatus. The read-only memory stores judgment codes. The multiplexer is controlled by the micro-process unit to switch to the interface control unit, the read-only memory or the random access memory. When the bus is not busy, the micro-process unit can read data from the memory apparatus. When the bus is occupied and busy, the micro-process unit can read and execute codes from the read-only memory or the random access memory so as to avoid computer system instability or thermal damage.

Abstract: A super input/output (I/O) module for controlling a universal serial bus (USB) port of a computer system is provided. The super I/O module includes a USB host, a switch and a processor. The switch selectively couples the USB port of the computer system to the USB host or a controller of the computer system according to a switching signal. When a trigger event occurs, the processor provides the switching signal to control the switch, so as to couple the USB port of the computer system to the USB host and to transmit a basic input/output system (BIOS) code to a flash memory of the computer system via the switch and the USB port.

Abstract: A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal.

Abstract: An embodiment of the invention provides a clock calibration method to calibrate an internal clock signal of a computer. The method comprises: receiving an external clock signal from an external clock source; generating a pulse signal with a first duration according to the external clock signal; counting the internal clock signal according to the pulse signal to get a first count value; and calibrating the internal clock according to the first count value.

Abstract: A super I/O module for controlling at least one I/O port of a computer system is provided. The super I/O module includes a controller, a signal detector and a selector. The controller supports functions corresponding to the I/O port. The signal detector receives an input signal from the I/O port, and detects whether the input signal has an identification code. When detecting that the input signal has the identification code, the signal detector generates a selection signal according to the identification code. The selector receives the selection signal and selectively provides the input signal to the controller or a function circuit of the computer system according to the selection signal.

Abstract: A global positioning system (GPS) log with low power consumption has an antenna, a GPS module, a power control module, a main control module, a power adjusting unit and a memory. The main control module is connected to the GPS module and the power control module to retrieve the computing results of the GPS module and controls the power control module to periodically provide power to the GPS module according to a predetermined and variable power providing period. The power adjusting unit is connected to the main control module, analyzes the computing results of the GPS module and assists the main control module to adjust the power providing period. Since the main control module automatically adjusts the power providing period, the GPS log does not deplete unnecessary power on the GPS module. Therefore, the power consumption of the GPS log is reduced and the GPS operates longer.

Abstract: A global positioning system (GPS) log with low power consumption has an antenna, a GPS module, a power control module, a main control module, a power adjusting unit and a memory. The main control module is connected to the GPS module and the power control module to retrieve the computing results of the GPS module and controls the power control module to periodically provide power to the GPS module according to a predetermined and variable power providing period. The power adjusting unit is connected to the main control module, analyzes the computing results of the GPS module and assists the main control module to adjust the power providing period. Since the main control module automatically adjusts the power providing period, the GPS log does not deplete unnecessary power on the GPS module. Therefore, the power consumption of the GPS log is reduced and the GPS operates longer.

Abstract: A cache/prefetch frame of serial data system and an operation method of the same. The cache/prefetch frame has a main controller, a main controller bus, a prefetch circuit, and a serial memory. The cache/prefetch frame of serial data system uses a serial interface between the main controller and the serial memory, such that the pins of the interface are decreased and consequently, the cost is reduced. The low-cost prefetch circuit is built in the main controller to overcome the drawback of the relatively low bandwidth between the main controller and the serial memory. The operation method of the cache/prefetch frame uses clock control to determine the timing for providing a clock signal to the main controller, such that bugs or shutdown caused by long waiting time of the main controller is prevented.

Abstract: Higher speed data transactions between a host computer's system memory and a plurality of slow peripheral devices are accomplished by providing distributed DMA functions along with distributed pre-fetch buffers. The first I/O device accesses the host bus via a first DMA channel and a first pre-fetch buffer, the second I/O device accesses the host bus via a second DMA channel and a second pre-fetch buffer, and the third I/O device accesses the host bus via a third DMA channel and a third pre-fetch buffer. In a first DMA transaction, the first pre-fetch buffer is filled with data being transferred between the first I/O device and the host system memory. While the data are transferred between the pre-fetch buffer and either the first I/O device or the system memory, the second pre-fetch buffer is being filled pursuant to a second DMA transaction between the second I/O device and the system memory.

Abstract: A computer system cache memory has a caching tag which stores a subset of the L2 cache memory tag store. The caching tag is smaller, faster memory device than the L2 cache memory. The cache memory latency is reduced because the tag access time and tag comparison time are improved due to the caching tag. The caching tag may be manufactured to be located on the same chip as the cache controller, which allows faster data access than if the caching tag is located on a separate chip.