Patents by Inventor Yueh-Yi Chen

Yueh-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10972840
    Abstract: A speaker includes a circuit board, a peripheral wall, a diaphragm, at least one support member and at least one piezoelectric actuator. The peripheral wall is located on a surface of the circuit board. The diaphragm has an outer boundary attached to the peripheral wall. The diaphragm, the peripheral wall and the circuit board collectively form a chamber. The at least one support member protrudes from the surface of the circuit board and is located within the chamber. The at least one piezoelectric actuator is located on a top of the at least one support member and electrically driven to cause a vibration of the diaphragm under applied electrical bias.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 6, 2021
    Assignee: MERRY ELECTRONICS (SHENZHEN) CO., LTD.
    Inventors: Jen-Yi Chen, Yueh-Kang Lee, Kai-Yu Jiang, Chao-Sen Chang
  • Publication number: 20200350113
    Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: Feng-Lung CHIEN, Tsang-Feng WU, Yuan HAN, Tzu-Chieh KAO, Chien-Hung LIN, Kuang-Lun LEE, Hsiang-Hui HSU, Shu-Yi TSUI, Kuo-Jui LEE, Kun-Ying LEE, Mao-Chun CHEN, Tai-Hsien YU, Wei-Yu CHEN, Yi-Ju LI, Kuei-Yuan CHANG, Wei-Chun LI, Ni-Ni LAI, Sheng-Hao LUO, Heng-Sheng PENG, Yueh-Hui KUAN, Hsiu-Chen LIN, Yan-Bing ZHOU, Chris T. Burket
  • Publication number: 20200289454
    Abstract: A method for suppressing tumor metastasis, in which an effective amount of a compound of formula (I) is administered to a subject in need thereof. Also disclosed is a method of treating cancer, in which an effective amount of a chemotherapy agent and an effective amount of a compound of formula (I) is administered to a subject in need thereof. Further disclosed are pharmaceutical compositions for suppressing tumor metastasis and for treating cancer, each of the compositions containing a compound of formula (I).
    Type: Application
    Filed: March 17, 2017
    Publication date: September 17, 2020
    Applicants: ACADEMIA, Sinica
    Inventors: Ning-Sun Yang, Yueh-Hsiung Kuo, Shu-Yi Yin, Yung-Hsiang Chen
  • Publication number: 20200177996
    Abstract: A speaker includes a circuit board, a peripheral wall, a diaphragm, at least one support member and at least one piezoelectric actuator. The peripheral wall is located on a surface of the circuit board. The diaphragm has an outer boundary attached to the peripheral wall. The diaphragm, the peripheral wall and the circuit board collectively form a chamber. The at least one support member protrudes from the surface of the circuit board and is located within the chamber. The at least one piezoelectric actuator is located on a top of the at least one support member and electrically driven to cause a vibration of the diaphragm under applied electrical bias.
    Type: Application
    Filed: June 26, 2019
    Publication date: June 4, 2020
    Inventors: Jen-Yi CHEN, Yueh-Kang LEE, Kai-Yu JIANG, Chao-Sen CHANG
  • Publication number: 20200152521
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10529629
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20190384185
    Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
  • Publication number: 20190371916
    Abstract: A semiconductor structure having a metal gate includes a dielectric layer. The dielectric layer having a recess is disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top. The present invention also provides a method of forming said semiconductor structure.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 5, 2019
    Inventors: Jing-Yi Lin, Yi-Wen Chen, Hung-Yi Wu, Ping-Wei Huang, Shao-Wei Wang, Yueh-Chi Chuang, Hung-Jen Huang, Hao-Che Feng
  • Publication number: 20190333826
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10361656
    Abstract: The present invention uses a power supply to splay a forward bias to a concentrating solar cell. Then the solar cell will emit red light (electroluminescence). After passing the secondary optical device packaged on the solar cell, the red light will exhibit specific light distribution. According to the light distribution, the accuracy of the packaging location of the solar cell, the forming precision of the secondary optical device, and whether the optical devices are defective can be examined.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: July 23, 2019
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.
    Inventors: Chun-Yi Chen, Yueh-Mu Lee, Hwen-Fen Hong
  • Patent number: 10361655
    Abstract: The present invention discloses an electrical inspection method for solar cells, comprising steps of supplying a voltage and a current to a solar cell for stimulating the solar cell and giving a ray of light; filtering the light to give a ray of light having a predetermined wavelength; and measuring an optical power value of the light having a predetermined wavelength. The electrical inspection method adopts a low-cost apparatus to replace the solar simulators according to the prior art. In addition to saving costly equipment, filter adjustment, and the maintenance fee for replacing lamps, the defect inspection flow for solar cells can be further integrated and hence improving the efficiency.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: July 23, 2019
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.
    Inventors: Yueh-Mu Lee, Chun-Yi Chen, Zun-Hao Shih, Hwen-Fen Hong
  • Publication number: 20190214943
    Abstract: The present invention uses a power supply to splay a forward bias to a concentrating solar cell. Then the solar cell will emit red light (electroluminescence). After passing the secondary optical device packaged on the solar cell, the red light will exhibit specific light distribution. According to the light distribution, the accuracy of the packaging location of the solar cell, the forming precision of the secondary optical device, and whether the optical devices are defective can be examined.
    Type: Application
    Filed: January 9, 2018
    Publication date: July 11, 2019
    Inventors: CHUN-YI CHEN, YUEH-MU LEE, HWEN-FEN HONG
  • Patent number: 10332477
    Abstract: A display device includes a display array and a driving circuit. The display array includes at least one scan line. The driving circuit drives the display array and includes a timing controller and a gate driver. The timing controller controls a refresh rate of the display array at a first frequency or a second frequency, where the first frequency is higher substantially than the second frequency. The gate driver switches between supplying an enable voltage signal and a disable voltage signal to the scan line. Under the first or frequency, a corresponding first or second voltage difference exists between the enable voltage signal and the disable voltage signal. The first voltage difference is substantially greater than the second voltage difference, and the enable voltage signal has a same enable period.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 25, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yueh-Hung Chung, Ya-Ling Hsu, Han-Ming Chen, Chen-Hsien Liao, Gang-Yi Lin, Wen-Chen Lo, Ming-Chang Shih, Hsueh-Ying Huang