Patents by Inventor Yueh-Yi Chen

Yueh-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11930318
    Abstract: An electronic device, including a first substrate, a partition wall structure, a pressurizing component, a second substrate, a shell, and multiple first conductive parts, is provided. The first substrate has a through hole, and a first surface and a second surface that are opposite to each other. The partition wall structure is disposed on the first surface and surrounds to form a first chamber. The pressurizing component is disposed on the partition wall structure and covers the first chamber. The pressurizing component includes at least a mass and a vibration membrane. The shell is disposed on the second substrate and jointly forms a second chamber with the second substrate. The first chamber is formed in the second chamber. The multiple first conductive parts are disposed between the first substrate and the second substrate. There is a gap between any two adjacent first conductive parts.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Merry Electronics Co., Ltd.
    Inventors: Yueh-Kang Lee, Jen-Yi Chen, Kai-Yu Jiang
  • Publication number: 20240079439
    Abstract: A pixel of an image sensor includes: a semiconductor material substrate; a photosensitive region formed in the substrate, the photosensitive region generating photo-induced electrical charge in response to illumination with light; a storage node formed in the substrate proximate to the photosensitive region, the storage node selectively receiving and storing photo-induced electrical charge generated by the photosensitive region; and a shield formed over the storage node which inhibits light from reaching the storage node, the shield including an extension which protrudes into the substrate and surrounds an outer periphery of the storage node.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 7, 2024
    Inventors: Chung-Yi Lin, Yueh-Chuan Lee, Chia-Chan Chen
  • Publication number: 20230359131
    Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 9, 2023
    Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
  • Patent number: 11762302
    Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
  • Patent number: 11295990
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20210278771
    Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
  • Patent number: 11016398
    Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
  • Publication number: 20200152521
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10529629
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20190384185
    Abstract: Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Inventors: Tseng Chin Lo, Bo-Sen Chang, Yueh-Yi Chen, Chih-Ting Sun, Ying-Jung Chen, Kung-Cheng Lin, Meng Lin Chang
  • Publication number: 20190333826
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang