Patents by Inventor Yueh-You Chen

Yueh-You Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8169014
    Abstract: System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: May 1, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yueh-You Chen, Chung-Long Chang, Chih-Ping Chao
  • Patent number: 7335956
    Abstract: A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor device, without occupying an extra layout area.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: February 26, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yueh-You Chen, Chung-Long Chang, Chih-Ping Chao, Chun-Hong Chen
  • Publication number: 20070158783
    Abstract: System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.
    Type: Application
    Filed: January 9, 2006
    Publication date: July 12, 2007
    Inventors: Yueh-You Chen, Chung-Long Chang, Chih-Ping Chao
  • Publication number: 20060180895
    Abstract: A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor device, without occupying an extra layout area.
    Type: Application
    Filed: February 11, 2005
    Publication date: August 17, 2006
    Inventors: Yueh-You Chen, Chung-Long Chang, Chih-Ping Chao, Chun-Hong Chen