Abstract: A semiconductor device, a preparation method thereof and a memory apparatus are provided. The semiconductor device includes a semiconductor substrate on which multiple strip-shaped stacked structures and a sidewall structure covering a periphery of each stacked structure are disposed, and a conductive structure is disposed on a side of the stacked structure far away from the semiconductor substrate. The stacked structure includes a conductor layer disposed on the semiconductor substrate and configured to transmit a data signal, an isolation layer disposed on a side of the conductor layer far away from the semiconductor substrate, a separation layer disposed on a side of the isolation layer far away from the semiconductor substrate and made of a low dielectric constant material, and a dielectric layer disposed on a side of the separation layer far away from the semiconductor substrate and configured to isolate the separation layer from the conductive structure.

Abstract: The present disclosure provides a method for forming semiconductor structure and a semiconductor structure. The method for forming semiconductor structure includes: providing a semiconductor base with a substrate and a first oxide material layer; wherein the first oxide material layer is arranged on the substrate, the first oxide material layer includes a first region and a second region located at edge of the first region; patterning and etching the first oxide material layer; wherein oxide line structures are formed, and an annular empty slot structure is formed; refilling a second material; wherein the second material in the first region forms a plurality of isolation line structures, and the second material in the second region forms an annular dummy isolation layer; removing the oxide line structure by patterning and etching, and forming through hole structures; and forming a conductive material layer in the through hole structures.

Abstract: A semiconductor device, a preparation method thereof and a memory apparatus are provided. The semiconductor device includes a semiconductor substrate on which multiple strip-shaped stacked structures and a sidewall structure covering a periphery of each stacked structure are disposed, and a conductive structure is disposed on a side of the stacked structure far away from the semiconductor substrate. The stacked structure includes a conductor layer disposed on the semiconductor substrate and configured to transmit a data signal, an isolation layer disposed on a side of the conductor layer far away from the semiconductor substrate, a separation layer disposed on a side of the isolation layer far away from the semiconductor substrate and made of a low dielectric constant material, and a dielectric layer disposed on a side of the separation layer far away from the semiconductor substrate and configured to isolate the separation layer from the conductive structure.

Abstract: A semiconductor structure is provided with a test region. In test region, the semiconductor structure includes a semiconductor substrate, a plurality of bit line contact structures arranged on semiconductor substrate and a plurality of wire groups. The semiconductor structure is provided with a plurality of separate active regions extending along a first direction. In first direction, each active region is electrically connected to two bit line contact structures. The plurality of wire groups are arranged along a second direction. Each wire group includes a plurality of wires extending along a third direction. In third direction, each of two bit line contact structures for each active region is connected to respective one of two bit line contact structures for active region adjacent to said each active region by a respective one of wires, so that two wire groups of the wire groups cooperate with each other to form a conductive path.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, the substrate is provided with memory cell array region and peripheral circuit region; a first insulating dielectric layer is formed in memory cell array region and a second insulating dielectric layer is formed in peripheral circuit region, bit line structures are formed in first insulating dielectric layer, conductive structures are formed in second insulating dielectric layer, each bit line structure includes a bit line conductive structure and an isolation structure covering a top and a side wall of bit line conductive structure; isolation structure is etched to form a first gap in memory cell array region and second insulating dielectric layer between conductive structures is etched to form a second gap in peripheral circuit region; and a third insulating dielectric layer is formed on a side wall of first gap and a side wall of second gap.