Patents by Inventor Yue Jun Zhang
Yue Jun Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315960Abstract: An SPUF based on combinational logic and scan chain comprises an external stimulus source, a combinational logic circuit module, a scan chain circuit module, a data processing module and n switch circuits SW0, SW1, . . . , SWn-1, n=2m, and m is an integer greater than or equal to 1; combinational logic circuit module comprises n switch circuits S0, S1, . . . , Sn-1 and a combinational logic circuit; the scan chain circuit module comprises n scan flip-flops (SFFs) SFF0, SFF1, . . . , SFFn-1; each of the n switch circuits SW0, SW1, . . . , SWn-1 and the n switch circuits S0, S1, . . . , Sn-1 is implemented by a 2-to-1 multiplexer. The SPUF based on combinational logic and scan chain has high uniqueness and randomness, requires a few clock frequency changes, and has high reliability, more bits of responses and high security.Type: ApplicationFiled: December 23, 2022Publication date: October 5, 2023Applicant: Wenzhou UniversityInventors: Pengjun WANG, Jia Chen, Yue Jun ZHANG, Gang LI, Youyi Zhuang
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Patent number: 11722131Abstract: An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit.Type: GrantFiled: November 23, 2020Date of Patent: August 8, 2023Assignee: Wenzhou UniversityInventors: Pengjun Wang, Hai Ming Zhang, Yue Jun Zhang, Gang Li, Bo Chen
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Publication number: 20230224171Abstract: Disclosed is a software PUF based on an RISC-V processor for IoT security. A 32-bit RISC-V processor is used to generate abnormal information results in an abnormal operating state under a low voltage, and the abnormal information results are used to represent the features of the 32-bit RISC-V processor; 5-bit binary data obtained by comparing the abnormal information results with normal information results has high randomness and uniqueness and it is extremely difficult to directly extract internal abnormal information result from a hardware circuit of the 32-bit RISC-V processor, so modeling attacks based on the 5-bit binary data calculated according to the abnormal information results of the 32-bit RISC-V processor are almost impossible; in addition, when the 32-bit RISC-V processor is in an abnormal operating state, the operating frequency of the 32-bit RISC-V processor is dynamically adjusted through a frequency compensation method.Type: ApplicationFiled: August 31, 2022Publication date: July 13, 2023Applicant: Wenzhou UniversityInventors: Pengjun WANG, Li Ni, Yue Jun ZHANG, Di Zhou, Yijian SHI
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Publication number: 20230085939Abstract: An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit.Type: ApplicationFiled: November 23, 2020Publication date: March 23, 2023Applicant: Wenzhou UniversityInventors: Pengjun WANG, Hai Ming ZHANG, Yue Jun ZHANG, Gang LI, Bo CHEN
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Publication number: 20230092828Abstract: A reliable multi-information entropy PUF for Internet of Things security includes a control circuit, a data register, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module. The control circuit controls the data register to generate a square signal, the 128 glitch generation circuits to generate glitch signals to be output and the 128-to-1 multiplexer to select the glitch signals to be output. The Schmidt glitch sampling module samples the glitch signals to obtain PUF response outputs. Each glitch generation circuit generates a glitch signal by means of a fully symmetrical structure. The Schmidt glitch sampling module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a buffer module and a D flip-flop.Type: ApplicationFiled: September 1, 2022Publication date: March 23, 2023Applicant: Wenzhou UniversityInventors: Pengjun WANG, Li Ni, Di Zhou, Yue Jun ZHANG, Bo CHEN, Xiaochun Guan
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Patent number: 8306178Abstract: The present invention discloses a vMOS based multi-valued counter unit. The counter unit includes a vMOS source follower and at least a control gate connected the vMOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the vMOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the vMOS follower. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE).Type: GrantFiled: June 5, 2012Date of Patent: November 6, 2012Assignee: Ningbo UniversityInventors: Peng Jun Wang, Yue Jun Zhang
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Publication number: 20120250817Abstract: The present invention discloses a ?MOS based multi-valued counter unit. The counter unit includes a ?MOS source follower and at least a control gate connected the ?MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the ?MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the ?MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption.Type: ApplicationFiled: June 5, 2012Publication date: October 4, 2012Applicant: NINGBO UNIVERSITYInventors: PENG JUN WANG, Yue Jun Zhang
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Patent number: 8218714Abstract: The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption.Type: GrantFiled: December 30, 2010Date of Patent: July 10, 2012Assignee: Ningbo UniversityInventors: Peng Jun Wang, Yue Jun Zhang
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Publication number: 20110158378Abstract: The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption.Type: ApplicationFiled: December 30, 2010Publication date: June 30, 2011Applicant: NINGBO UNIVERSITYInventors: Peng Jun Wang, Yue Jun Zhang