Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: A preparation method for covalent organic framework 5 (COF-5) includes: adding 2,3,6,7,10,11-hexahydroxytriphenylene and 1,4-phenylenebisboronic acid to a mixed solution of 1,3,5-trimethylbenzene and 1,4-dioxane to form a mixture in the anhydrous and oxygen-free environment; and the addition ratio of 2,3,6,7,10,11-hexahydroxytriphenylene:1,4-phenylenebisboronic acid:1,3,5-trimethylbenzene:1,4-dioxane is 0.02-0.8 mmol:0.08-1.4 mmol:10-15 mL:10-15 mL; sealing the mixture in an airtight container; and obtaining a uniform dispersion solution after shaking the container for wholly mixing the components; heating the dispersion solution to a temperature ranging from 80-100° C.; reacting for a period of time ranging from 72-120 h; and obtaining a precipitate after the reaction; and washing the precipitate, drying the precipitate in vacuum, and heating the precipitate at a temperature ranging from 200-300° C. for a period of time ranging from 1-3 h with a protective atmosphere to obtain COF-5 crystal.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: A preparation method for covalent organic framework 5 (COF-5) includes: adding 2,3,6,7,10,11-hexahydroxytriphenylene and 1,4-phenylenebisboronic acid to a mixed solution of 1,3,5-trimethylbenzene and 1,4-dioxane to form a mixture in the anhydrous and oxygen-free environment; and the addition ratio of 2,3,6,7,10,11-hexahydroxytriphenylene: 1,4-phenylenebisboronic acid: 1,3,5-trimethylbenzene: 1,4-dioxane is 0.02-0.8 mmol: 0.08-1.4 mmol: 10-15 mL: 10-15 mL; sealing the mixture in an airtight container; and obtaining a uniform dispersion solution after shaking the container for wholly mixing the components; heating the dispersion solution to a temperature ranging from 80-100° C.; reacting for a period of time ranging from 72-120 h; and obtaining a precipitate after the reaction; and washing the precipitate, drying the precipitate in vacuum, and heating the precipitate at a temperature ranging from 200-300° C. for a period of time ranging from 1-3 h with a protective atmosphere to obtain COF-5 crystal.

Abstract: Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In).

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In).

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with passive device pads and package assemblies and systems incorporating such coreless substrates. A coreless substrate may comprise a plurality of build-up layers, such as bumpless build-up layers (BBUL). In various embodiments, electrical routing features and passive device pads may be disposed on an outer surface of the substrate. In various embodiments, the passive device pads may be coupled with a conductive element disposed on or within the build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power between the passive device pads and a die coupled to the coreless substrate.

Abstract: Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material. In some embodiments, an apparatus includes an electrical element (such as a die or a bridge interconnect structure) positioned on a surface of an insulator layer, a conductive pad positioned on the surface of the insulator layer and spaced apart from the electrical element, and a molded insulator material disposed on the surface of the insulator layer adjacent to the electrical element and on the conductive pad. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material. In some embodiments, an apparatus includes an electrical element (such as a die or a bridge interconnect structure) positioned on a surface of an insulator layer, a conductive pad positioned on the surface of the insulator layer and spaced apart from the electrical element, and a molded insulator material disposed on the surface of the insulator layer adjacent to the electrical element and on the conductive pad. Other embodiments may be described and/or claimed.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.