Patents by Inventor Yueming Jiang

Yueming Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Duty cycle calibration for receiver clock
    Patent number: 7668698
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: February 23, 2010
    Assignee: Intel Corporation
    Inventor: Yueming Jiang
  • Eliminating receiver clock drift caused by voltage and temperature change in a high-speed I/O system that uses a forwarded clock
    Patent number: 7571340
    Abstract: Integrated circuits include clock deskew circuitry. The clock deskew circuitry, at the receiver side, receives data signals and a forwarded clock signal from a transmitter. The receiver detects a clock drift in a receiver clock tree, and transmits the detected clock drift to the transmitter. Based on the detected clock drift, the transmitter adjusts the timing of the transmitted signals so that the center of the data eye is aligned with the clock edge at the output of the receiver clock tree.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: August 4, 2009
    Assignee: Intel Corporation
    Inventor: Yueming Jiang
  • Apparatus, system, and method for bitwise deskewing
    Publication number: 20090168563
    Abstract: A system and method for bitwise deskew. A DQS timing is used as reference, the delays of a plurality of transmission wires are calibrated with reference to a DQS line timing. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventor: Yueming Jiang
  • DUTY CYCLE CALIBRATION FOR RECEIVER CLOCK
    Publication number: 20090146715
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 11, 2009
    Inventor: YUEMING JIANG
  • Eliminating receiver clock drift caused by voltage and temperature change in a high-speed I/O system that uses a fowarded clock
    Publication number: 20070286320
    Abstract: Integrated circuits include clock deskew circuitry. The clock deskew circuitry, at the receiver side, receives data signals and a forwarded clock signal from a transmitter. The receiver detects a clock drift in a receiver clock tree, and transmits the detected clock drift to the transmitter. Based on the detected clock drift, the transmitter adjusts the timing of the transmitted signals so that the center of the data eye is aligned with the clock edge at the output of the receiver clock tree.
    Type: Application
    Filed: June 13, 2006
    Publication date: December 13, 2007
    Inventor: Yueming Jiang