Abstract: A device includes a comparator having a first comparator input configured to receive a time signal. The device also includes a subtractor having a subtractor output coupled to a second comparator input, and a first subtractor input adapted to be coupled to a voltage converter terminal. The device also includes a current source having an output coupled to a second subtractor input, and a current source input coupled to the first subtractor input. The device also includes a capacitor coupled to the second subtractor input and to ground. The device also includes a latch having an output and first and second inputs. The latch output is coupled to a control terminal of a transistor in parallel with the capacitor, the first latch input is coupled to the comparator output, and the second latch input is configured to receive a clock signal.

Abstract: A device includes a first FET coupled between first and drive terminals, and is configured to turn on/off responsive to a PWM signal having a first/second state, respectively. A second FET is coupled between the first and drive terminals and is configured to turn on responsive to the PWM signal having the first state, and turn off responsive to expiration of a particular delay after the second FET turns on. A third FET is coupled between drive and second terminals, and is configured to turn on/off responsive to the PWM signal having the second/first state, respectively. A fourth FET is coupled between the drive and second terminals, and is configured to turn on responsive to the PWM signal having the second state if a switching terminal has a first voltage, and turn off responsive to the PWM signal having the first state or the switching terminal having a second voltage.

Abstract: An allulose 3-epimerase mutant, a genetically engineered bacterium expressing the mutant, and an immobilized allulose 3-epimerase enzyme and an immobilization method thereof are described. A high-throughput screening method is used to obtain an allulose 3-epimerase mutant efficiently expressed in a fermentation process, which can catalyze efficient conversion of fructose to D-allulose, providing an efficient production path for key enzymes required in a D-allulose production process. Additionally, the allulose 3-epimerase is bonded to an immobilizing resin to prepare an immobilized allulose 3-epimerase enzyme. The immobilized enzyme can be applied to batch or continuous reactions to catalyze efficient conversion of fructose to D-allulose.

Abstract: The present invention relates to a dioxinoquinoline compound of formula (I) or a pharmaceutically acceptable salt thereof. The invention also provides a preparation method of the compound of formula (I) and a pharmaceutically acceptable salt thereof, as well as uses thereof as a drug, wherein the drug acting as a tyrosine kinase (i.e. VEGFR-2 and c-MET) inhibitor is used for treating disorders related to tyrosine kinase.

Abstract: Disclosed are a class of compounds as inhibitors of kinases such as TRK, c-MET, AXL, MER and/or VEGFR2, compositions and use thereof. In particular, disclosed are a class of compounds (as shown in formula (1)) or isomers, solvates, hydrates, pharmaceutically acceptable salts, and prodrugs thereof having strong inhibition activities for kinases such as TRK, c-MET, AXL, MER and/or VEGFR2, and pharmaceutical compositions comprising said compounds. Also disclosed is use of the compounds or pharmaceutical compositions in the preparation of a medicament for treating autoimmune diseases or cancers.

Abstract: A device includes a first FET coupled between first and drive terminals, and is configured to turn on/off responsive to a PWM signal having a first/second state, respectively. A second FET is coupled between the first and drive terminals and is configured to turn on responsive to the PWM signal having the first state, and turn off responsive to expiration of a particular delay after the second FET turns on. A third FET is coupled between drive and second terminals, and is configured to turn on/off responsive to the PWM signal having the second/first state, respectively. A fourth FET is coupled between the drive and second terminals, and is configured to turn on responsive to the PWM signal having the second state if a switching terminal has a first voltage, and turn off responsive to the PWM signal having the first state or the switching terminal having a second voltage.

Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.

Abstract: A circuit includes a power stage circuit configured to perform power conversion of an input voltage to provide an output voltage at an output. The circuit further includes a driver circuit configured to drive the power stage circuit to provide the output voltage. The circuit further includes a load transient dynamic compensator configured to detect a rate of change in the output voltage during load transient and to supply a compensating signal based on the rate of change. The circuit further includes a feedback control circuit configured to generate a series of pulses to control the driver circuit based on the output voltage and the compensating signal.

Abstract: The present invention relates to a dioxinoquinoline compound of formula (I) or a pharmaceutically acceptable salt thereof. The invention also provides a preparation method of the compound of formula (I) and a pharmaceutically acceptable salt thereof, as well as uses thereof as a drug, wherein the drug acting as a tyrosine kinase (i.e. VEGFR-2 and c-MET) inhibitor is used for treating disorders related to tyrosine kinase.

Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.

Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.

Abstract: A circuit includes a power stage circuit configured to perform power conversion of an input voltage to provide an output voltage at an output. The circuit further includes a driver circuit configured to drive the power stage circuit to provide the output voltage. The circuit further includes a load transient dynamic compensator configured to detect a rate of change in the output voltage during load transient and to supply a compensating signal based on the rate of change. The circuit further includes a feedback control circuit configured to generate a series of pulses to control the driver circuit based on the output voltage and the compensating signal.

Abstract: An apparatus comprises a voltage supply configured to provide an input voltage, a buck-boost converter coupled to the voltage supply and comprising an inductor, and a buck-boost controller coupled to the power supply and the buck-boost converter. The buck-boost controller comprises a mode controller coupled to the buck-boost converter and a comparator coupled to the mode controller and the buck-boost converter. The comparator is configured to compare an error signal based on an output voltage of the buck boost-converter to an output current of the inductor to produce a control signal. The mode controller is configured to control the output voltage at least in part according to the control signal.

Abstract: An apparatus comprises a voltage supply configured to provide an input voltage, a buck-boost converter coupled to the voltage supply and comprising an inductor, and a buck-boost controller coupled to the power supply and the buck-boost converter. The buck-boost controller comprises a mode controller coupled to the buck-boost converter and a comparator coupled to the mode controller and the buck-boost converter. The comparator is configured to compare an error signal based on an output voltage of the buck boost-converter to an output current of the inductor to produce a control signal. The mode controller is configured to control the output voltage at least in part according to the control signal.

Abstract: The present teaching relates to developing a virtual agent. In one example, a plurality of graphical objects is presented to a user via a bot design programming interface. Each of the plurality of graphical objects represents a module corresponding to an action to be performed by the virtual agent. One or more inputs from the user are received, via the bot design programming interface, for selecting a set of graphical objects from the plurality of graphical objects. The one or more inputs provide information of a first order of the set of graphical objects. A plurality of modules represented by the set of graphical objects is identified. Based on the one or more inputs, a second order of the plurality of modules is determined based on the first order. The plurality of modules is integrated in the second order to generate a customized virtual agent for executing an associated task according to the second order.