Abstract: A cyano-substituted pyridine and cyano-substituted pyrimidine compound and a preparation method therefor and an application thereof, which specifically relate to a compound represented by formula (I) and an isomer, a hydrate, a solvate, a pharmaceutically acceptable salt, and a prodrug thereof, and a preparation method therefor and an application thereof in the preparation of a drug as a kinase inhibitor. The compound has good inhibitory activity against kinases such as FGFR4 and mutant FGFR4V550L.

Abstract: A circuit includes an amplifier, a capacitor, a resistor, a voltage controlled current source (VCCS), and a differentiator circuit. The amplifier has a feedback input, a reference input, and an error output. The capacitor has a first capacitor terminal coupled to the error output, and second capacitor terminal. The resistor has a first resistor terminal coupled to the second capacitor terminal, and a second resistor terminal. The VCCS has a first terminal coupled to the first capacitor terminal, a second terminal coupled to the second resistor terminal, and a VCCS input. The differentiator circuit has an input coupled to the second resistor terminal, and an output coupled to the VCCS input.

Abstract: Current balancing techniques. In an example, a circuit includes a synchronization terminal, an error amplifier, and a clock generator. The error amplifier is configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage. The clock generator is configured to produce an outgoing clock signal having an outgoing clock frequency. The circuit further includes an encoder, a frequency detector, and a decoder. The encoder is coupled to the clock generator and synchronization terminal, and configured to encode the outgoing clock signal based on the first control voltage signal to provide, at synchronization terminal, an outgoing encoded clock signal. The frequency detector is coupled to synchronization terminal and configured to derive, from an incoming encoded clock signal, an incoming clock frequency. The decoder is coupled to synchronization terminal and configured to derive, from the incoming encoded clock signal, a second control voltage signal.

Abstract: Disclosed are a class of compounds as inhibitors of kinases such as TRK, c-MET, AXL, MER and/or VEGFR2, compositions and use thereof. In particular, disclosed are a class of compounds (as shown in formula (1)) or isomers, solvates, hydrates, pharmaceutically acceptable salts, and prodrugs thereof having strong inhibition activities for kinases such as TRK, c-MET, AXL, MER and/or VEGFR2, and pharmaceutical compositions comprising said compounds. Also disclosed is use of the compounds or pharmaceutical compositions in the preparation of a medicament for treating autoimmune diseases or cancers.

Abstract: Provided are a quinazoline compound, a composition, and an application thereof, in particular, a compound represented by formula (I), a stereoisomer thereof, a pharmaceutically acceptable salt thereof, a composition thereof, and an application thereof in the preparation for a drug that serves as a tyrosine kinase inhibitor. The compound represented by formula (I) has good inhibitory activity against EGFR and HER2 kinases.

Abstract: Described embodiments include a voltage converter power circuit having a high-voltage rated first transistor with a first current terminal coupled to an input voltage terminal, and a second current terminal. A second transistor, a low-voltage rated transistor, has a second control terminal, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a switching terminal. A third transistor, a high-voltage rated transistor, has a fifth current terminal coupled to the switching terminal, a sixth current terminal, and a third control terminal. A fourth transistor, a low-voltage rated transistor, is coupled between the sixth current terminal and a ground terminal. A bleeder circuit is coupled between the seventh and eighth current terminals and is configured to prevent a voltage across the fourth transistor from exceeding a breakdown voltage.

Abstract: A cyano-substituted pyridine and cyano-substituted pyrimidine compound and a preparation method therefor and an application thereof, which specifically relate to a compound represented by formula (I) and an isomer, a hydrate, a solvate, a pharmaceutically acceptable salt, and a prodrug thereof, and a preparation method therefor and an application thereof in the preparation of a drug as a kinase inhibitor. The compound has good inhibitory activity against kinases such as FGFR4 and mutant FGFR4V550L.

Abstract: A device includes a comparator having a first comparator input configured to receive a time signal. The device also includes a subtractor having a subtractor output coupled to a second comparator input, and a first subtractor input adapted to be coupled to a voltage converter terminal. The device also includes a current source having an output coupled to a second subtractor input, and a current source input coupled to the first subtractor input. The device also includes a capacitor coupled to the second subtractor input and to ground. The device also includes a latch having an output and first and second inputs. The latch output is coupled to a control terminal of a transistor in parallel with the capacitor, the first latch input is coupled to the comparator output, and the second latch input is configured to receive a clock signal.

Abstract: A device includes a first FET coupled between first and drive terminals, and is configured to turn on/off responsive to a PWM signal having a first/second state, respectively. A second FET is coupled between the first and drive terminals and is configured to turn on responsive to the PWM signal having the first state, and turn off responsive to expiration of a particular delay after the second FET turns on. A third FET is coupled between drive and second terminals, and is configured to turn on/off responsive to the PWM signal having the second/first state, respectively. A fourth FET is coupled between the drive and second terminals, and is configured to turn on responsive to the PWM signal having the second state if a switching terminal has a first voltage, and turn off responsive to the PWM signal having the first state or the switching terminal having a second voltage.

Abstract: The present invention relates to a dioxinoquinoline compound of formula (I) or a pharmaceutically acceptable salt thereof. The invention also provides a preparation method of the compound of formula (I) and a pharmaceutically acceptable salt thereof, as well as uses thereof as a drug, wherein the drug acting as a tyrosine kinase (i.e. VEGFR-2 and c-MET) inhibitor is used for treating disorders related to tyrosine kinase.

Abstract: Disclosed are a class of compounds as inhibitors of kinases such as TRK, c-MET, AXL, MER and/or VEGFR2, compositions and use thereof. In particular, disclosed are a class of compounds (as shown in formula (1)) or isomers, solvates, hydrates, pharmaceutically acceptable salts, and prodrugs thereof having strong inhibition activities for kinases such as TRK, c-MET, AXL, MER and/or VEGFR2, and pharmaceutical compositions comprising said compounds. Also disclosed is use of the compounds or pharmaceutical compositions in the preparation of a medicament for treating autoimmune diseases or cancers.

Abstract: A device includes a first FET coupled between first and drive terminals, and is configured to turn on/off responsive to a PWM signal having a first/second state, respectively. A second FET is coupled between the first and drive terminals and is configured to turn on responsive to the PWM signal having the first state, and turn off responsive to expiration of a particular delay after the second FET turns on. A third FET is coupled between drive and second terminals, and is configured to turn on/off responsive to the PWM signal having the second/first state, respectively. A fourth FET is coupled between the drive and second terminals, and is configured to turn on responsive to the PWM signal having the second state if a switching terminal has a first voltage, and turn off responsive to the PWM signal having the first state or the switching terminal having a second voltage.

Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.

Abstract: A circuit includes a power stage circuit configured to perform power conversion of an input voltage to provide an output voltage at an output. The circuit further includes a driver circuit configured to drive the power stage circuit to provide the output voltage. The circuit further includes a load transient dynamic compensator configured to detect a rate of change in the output voltage during load transient and to supply a compensating signal based on the rate of change. The circuit further includes a feedback control circuit configured to generate a series of pulses to control the driver circuit based on the output voltage and the compensating signal.

Abstract: The present invention relates to a dioxinoquinoline compound of formula (I) or a pharmaceutically acceptable salt thereof. The invention also provides a preparation method of the compound of formula (I) and a pharmaceutically acceptable salt thereof, as well as uses thereof as a drug, wherein the drug acting as a tyrosine kinase (i.e. VEGFR-2 and c-MET) inhibitor is used for treating disorders related to tyrosine kinase.

Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.

Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage to an output voltage provided at an output, and a control circuit configured to control the power stage circuit. The control circuit is configured to operate in one of a pulse frequency modulation (“PFM”) mode and a pulse width modulation (“PWM”) mode depending on a current supplied to the output. The control circuit includes a multi-mode timer circuit configured to provide a switching signal to set an off time for each switching cycle of the power stage circuit during the PFM mode and during the PWM mode.

Abstract: A circuit includes a power stage circuit configured to perform power conversion of an input voltage to provide an output voltage at an output. The circuit further includes a driver circuit configured to drive the power stage circuit to provide the output voltage. The circuit further includes a load transient dynamic compensator configured to detect a rate of change in the output voltage during load transient and to supply a compensating signal based on the rate of change. The circuit further includes a feedback control circuit configured to generate a series of pulses to control the driver circuit based on the output voltage and the compensating signal.

Abstract: An apparatus comprises a voltage supply configured to provide an input voltage, a buck-boost converter coupled to the voltage supply and comprising an inductor, and a buck-boost controller coupled to the power supply and the buck-boost converter. The buck-boost controller comprises a mode controller coupled to the buck-boost converter and a comparator coupled to the mode controller and the buck-boost converter. The comparator is configured to compare an error signal based on an output voltage of the buck boost-converter to an output current of the inductor to produce a control signal. The mode controller is configured to control the output voltage at least in part according to the control signal.

Abstract: An apparatus comprises a voltage supply configured to provide an input voltage, a buck-boost converter coupled to the voltage supply and comprising an inductor, and a buck-boost controller coupled to the power supply and the buck-boost converter. The buck-boost controller comprises a mode controller coupled to the buck-boost converter and a comparator coupled to the mode controller and the buck-boost converter. The comparator is configured to compare an error signal based on an output voltage of the buck boost-converter to an output current of the inductor to produce a control signal. The mode controller is configured to control the output voltage at least in part according to the control signal.