Abstract: Examples of techniques for hang detection and recovery are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: sending, by a processor, a read request to a controller; detecting, by a data hang detection circuit, the read request; initiating, by the data hang detection circuit, a counter when the read request is first detected; monitoring, by the data hang detection circuit, to receive a read response from the controller; and responsive to the counter reaching a timeout threshold before receiving the read response, sending, by the data hang detection circuit a timeout error to the processor via a multiplexer in the data hang detection circuit.

Abstract: Examples of techniques for hang detection and recovery are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: sending, by a processor, a read request to a controller; detecting, by a data hang detection circuit, the read request; initiating, by the data hang detection circuit, a counter when the read request is first detected; monitoring, by the data hang detection circuit, to receive a read response from the controller; and responsive to the counter reaching a timeout threshold before receiving the read response, sending, by the data hang detection circuit a timeout error to the processor via a multiplexer in the data hang detection circuit.

Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.