Patents by Inventor Yuen Fai A. Wong
Yuen Fai A. Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110235518Abstract: Congestion control techniques based upon resource utilization information stored by a network device. According to an embodiment of the present invention, a network device is configured to identify a data source causing congestion based upon information stored by the network device identifying a set of data sources, and for each data source, information identifying the amount of a resource of the network device being used for processing data received by the network device from the data source.Type: ApplicationFiled: June 8, 2011Publication date: September 29, 2011Applicant: Brocade Communications Systems, Inc.Inventors: Mitri Halabi, Yuen Fai Wong, Robert Colvin, Frank S. Yang
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Patent number: 7995580Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.Type: GrantFiled: March 9, 2009Date of Patent: August 9, 2011Assignee: Foundry Networks, Inc.Inventors: Ronak Patel, Ming G. Wong, Yu-Mei Lin, Andrew Chang, Yuen Fai Wong
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Publication number: 20110182294Abstract: One embodiment provides a system that performs in-order traffic aggregation from a number of low-speed ports to a high-speed port. During operation, the system receives at a low-speed port a packet, stores it in a store-and-forward FIFO associated with the low-speed port, extracts a sequence number associated with the stored packet, and stores the extracted sequence number in a sequence-number FIFO associated with the low-speed port. The system further generates an expected sequence number, which maintains a linear order with respect to sequence numbers associated with previously forwarded packets, and determines whether a front end of the sequence-number FIFO matches the expected sequence number. If so, the system removes the front end of the sequence-number FIFO buffer, retrieves a packet associated with it, forwards the retrieved packet on the high-speed port, and updates the expected sequence number by adding 1 to the packet number of the retrieved packet.Type: ApplicationFiled: January 28, 2010Publication date: July 28, 2011Applicant: BROCADE COMMUNICATIONS SYSTEMS, INC.Inventors: Daniel Sangyoung Lee, Yuen Fai Wong
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Patent number: 7978607Abstract: Congestion control techniques based upon resource utilization information stored by a network device. According to an embodiment of the present invention, a network device is configured to identify a data source causing congestion based upon information stored by the network device identifying a set of data sources, and for each data source, information identifying the amount of a resource of the network device being used for processing data received by the network device from the data source.Type: GrantFiled: March 26, 2009Date of Patent: July 12, 2011Assignee: Brocade Communications Systems, Inc.Inventors: Mitri Halabi, Yuen Fai Wong, Robert Colvin, Frank S. Yang
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Patent number: 7948872Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.Type: GrantFiled: March 9, 2009Date of Patent: May 24, 2011Assignee: Foundry Networks, LLCInventors: Ronak Patel, Ming G. Wong, Yu-Mei Lin, Andrew Chang, Yuen Fai Wong
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Publication number: 20110110237Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.Type: ApplicationFiled: September 13, 2010Publication date: May 12, 2011Applicant: Foundry Networks, LLCInventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier
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Patent number: 7817659Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.Type: GrantFiled: March 26, 2004Date of Patent: October 19, 2010Assignee: Foundry Networks, LLCInventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier
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Publication number: 20100061393Abstract: The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures.Type: ApplicationFiled: October 29, 2009Publication date: March 11, 2010Applicant: Foundry Networks, Inc.Inventor: Yuen Fai Wong
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Publication number: 20100046521Abstract: The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures.Type: ApplicationFiled: October 29, 2009Publication date: February 25, 2010Applicant: Foundry Networks, Inc.Inventor: Yuen Fai Wong
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Publication number: 20100034215Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.Type: ApplicationFiled: July 17, 2009Publication date: February 11, 2010Applicant: Foundry Networks, Inc.Inventors: Ronak Patel, Ming G. Wong, Yu-mei Lin, Andrew Chang, Yuen Fai A. Wong
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Patent number: 7636369Abstract: The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures.Type: GrantFiled: November 29, 2004Date of Patent: December 22, 2009Assignee: Foundry Networks, Inc.Inventor: Yuen Fai Wong
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Publication number: 20090290499Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.Type: ApplicationFiled: March 9, 2009Publication date: November 26, 2009Applicant: Foundry Networks, Inc.Inventors: Ronak Patel, Ming G. Wong, Yu-mei Lin, Andrew Chang, Yuen Fai Wong
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Publication number: 20090287952Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.Type: ApplicationFiled: March 9, 2009Publication date: November 19, 2009Applicant: Foundry Networks, Inc.Inventors: Ronak Patel, Ming G. Wong, Yu-mei Lin, Andrew Z. Chang, Yuen Fai A. Wong
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Publication number: 20090279559Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.Type: ApplicationFiled: March 26, 2004Publication date: November 12, 2009Inventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier
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Patent number: 6901072Abstract: The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures.Type: GrantFiled: May 15, 2003Date of Patent: May 31, 2005Assignee: Foundry Networks, Inc.Inventor: Yuen Fai Wong