Abstract: The solution can provide a switch-configurable diplexer architecture for dual-band communication. A first diplexer can have a first band for an interlink connection between an access point and a device and a second band for an intralink connection between the device and a second device. The first band and the pass band can be separated by a first gap. A second diplexer can have a third band for the first interlink and a fourth band for the intralink. The third band and the fourth band can be separated by a second gap. The first band and the third band, as well as the second band and the fourth band, can partially overlap. A processor can identify that the access point has selected, for the interlink connection, a first channel corresponding to the second gap and determine, responsive to the identification, to use the second diplexer for the intralink connection.

Abstract: The disclosed systems and mobile electronic devices may include a capsule that houses various electronic components. These systems may also include a cradle that is configured to removably couple with the capsule. Still further, these systems may include a strap connected to a first end of the cradle. The strap itself may include at least one antenna. The systems may also include a radio frequency (RF) transparent interconnect that electrically connects the antenna in the strap to at least one of the electronic components in the capsule. Various other methods of manufacturing, systems, and apparatuses are also disclosed.

Abstract: An IQ generator capable of consuming lower power and occupying smaller die area. The IQ generator is configured without any synthesizer and divide-by-2 circuitry. The IQ generator may be configured to convert one or more phase outputs of a test tone generator (TTG) into I and Q signals. The IQ generator may receive as inputs differential outputs of a single phase of a TTG and/or multiple phase outputs of a TTG. The IQ generator may include one or more delay paths configured to generate the I and Q signals, and a calibration circuitry configured to compare the average pulse widths of the I and Q signals and provide one or more control signals to the one or more delay paths such that the I and Q signals are orthogonal in phase.

Abstract: An IQ generator capable of consuming lower power and occupying smaller die area. The IQ generator is configured without any synthesizer and divide-by-2 circuitry. The IQ generator may be configured to convert one or more phase outputs of a test tone generator (TTG) into I and Q signals. The IQ generator may receive as inputs differential outputs of a single phase of a TTG and/or multiple phase outputs of a TTG. The IQ generator may include one or more delay paths configured to generate the I and Q signals, and a calibration circuitry configured to compare the average pulse widths of the I and Q signals and provide one or more control signals to the one or more delay paths such that the I and signals are orthogonal in phase.

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Abstract: The isolated port of a 0/90 degree coupler is terminated by a novel complex termination impedance circuit having a reactance. The absolute value of the reactance is at least two ohms. The coupler receives a signal on its input port, and outputs a first signal on its first output port and a second signal on its second output port. A first load is coupled to the first output port without an intervening matching network. A substantial impedance mismatch exists between the first output port and the first load. A second load is coupled to the second output port without an intervening matching network. A substantial impedance mismatch exists between the second output port and the second load. Despite the substantial impedance mismatches, the first and second signals have a phase difference in a range of from 88 degrees to 92 degrees while exhibiting an amplitude imbalance less than 2 dB.

Abstract: A Radio Frequency (RF) front end system and method are disclosed. The RF front end system comprises an antenna, a matching network coupled to the antenna, a power amplifier (PA) coupled to the matching network via a port on a transmit path, a low noise amplifier (LNA) coupled to the matching network via the port on a receive path and at least one transmit/receive switch (T/R SW) coupled between the port and at least one of the PA and LNA.

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Abstract: The isolated port of a 0/90 degree coupler is terminated by a novel complex termination impedance circuit having a reactance. The absolute value of the reactance is at least two ohms. The coupler receives a signal on its input port, and outputs a first signal on its first output port and a second signal on its second output port. A first load is coupled to the first output port without an intervening matching network. A substantial impedance mismatch exists between the first output port and the first load. A second load is coupled to the second output port without an intervening matching network. A substantial impedance mismatch exists between the second output port and the second load. Despite the substantial impedance mismatches, the first and second signals have a phase difference in a range of from 88 degrees to 92 degrees while exhibiting an amplitude imbalance less than 2 dB.

Abstract: A Radio Frequency (RF) front end system and method are disclosed. The RF front end system comprises an antenna, a matching network coupled to the antenna, a power amplifier (PA) coupled to the matching network via a port on a transmit path, a low noise amplifier (LNA) coupled to the matching network via the port on a receive path and at least one transmit/receive switch (T/R SW) coupled between the port and at least one of the PA and LNA.

Abstract: A Radio Frequency (RF) front end system and method are disclosed. The RF front end system comprises an antenna, a matching network coupled to the antenna, a power amplifier (PA) coupled to the matching network via a port on a transmit path, a low noise amplifier (LNA) coupled to the matching network via the port on a receive path and at least one transmit/receive switch (T/R SW) coupled between the port and at least one of the PA and LNA.

Abstract: A Radio Frequency (RF) front end system and method are disclosed. The RF front end system comprises an antenna, a matching network coupled to the antenna, a power amplifier (PA) coupled to the matching network via a port on a transmit path, a low noise amplifier (LNA) coupled to the matching network via the port on a receive path and at least one transmit/receive switch (T/R SW) coupled between the port and at least one of the PA and LNA.

Abstract: A hybrid circuit (42) for use with communications transceivers. The hybrid circuit (42) combines the function of an ESD protection circuit (12) with the function of a TX/RX switch (10). The input node of the hybrid circuit (42) is connecting between the source of an ESD event (60) and a device to be protected (44). The hybrid circuit (42) includes an ESD protection element (50), which is triggered by a triggering transistor (52). The gate of the triggering transistor (52) is connected to a driver (54) for turning the triggering transistor (52) on during transmission and for turning the triggering transistor (52) off during reception.

Abstract: A biasing scheme for compensating for a difference in biasing currents between a first circuit element (10) and second circuit element (32) in a stacked circuit configuration. A current-difference source (38) generates a difference current that is substantially equal to the difference between the biasing currents of the first circuit element (10) and second circuit element (32) in order to compensate for process, temperature and supply variations.

Abstract: A hybrid circuit (42) for use with communications transceivers. The hybrid circuit (42) combines the function of an ESD protection circuit (12) with the function of a TX/RX switch (10). The input node of the hybrid circuit (42) is connecting between the source of an ESD event (60) and a device to be protected (44). The hybrid circuit (42) includes an ESD protection element (50), which is triggered by a triggering transistor (52). The gate of the triggering transistor (52) is connected to a driver (54) for turning the triggering transistor (52) on during transmission and for turning the triggering transistor (52) off during reception.