Patents by Inventor Yuezhong Du

Yuezhong Du has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Generating a wafer inspection process using bit failures and virtual inspection
    Patent number: 10014229
    Abstract: Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the water into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: July 3, 2018
    Assignee: KLA-Tencor Corp.
    Inventors: Poh Boon Yong, George Simon, Yuezhong Du
  • Generating a Wafer Inspection Process Using Bit Failures and Virtual Inspection
    Publication number: 20160163606
    Abstract: Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the water into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations.
    Type: Application
    Filed: February 10, 2016
    Publication date: June 9, 2016
    Inventors: Poh Boon Yong, George Simon, Yuezhong Du
  • Generating a wafer inspection process using bit failures and virtual inspection
    Patent number: 9277186
    Abstract: Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: March 1, 2016
    Assignee: KLA-Tencor Corp.
    Inventors: Poh Boon Yong, George Simon, Yuezhong Du