Abstract: A memory circuit includes an operational amplifier configured to generate a bias voltage at an output terminal responsive to reference and feedback voltages received at respective first and second input terminals, a first NMOS device including a gate coupled to the output terminal of the operational amplifier, a second NMOS device including a gate coupled to a source terminal of the first NMOS device and a source terminal coupled to the second input terminal of the operational amplifier, a resistive device coupled between the source terminal of the second NMOS device and a power reference node, a third NMOS device including a gate coupled to the output terminal of the operational amplifier, a fourth NMOS device including a gate coupled to a source terminal of the third NMOS device, and a resistance-based memory device coupled between a source terminal of the fourth NMOS device and the power reference node.

Abstract: A memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. The first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.

Abstract: A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

Abstract: A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

Abstract: A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.

Abstract: A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.

Abstract: A syringe is provided, including a syringe barrel, a needle set and a push rod. A front end part is provided in the syringe barrel. An end of the needle set has an open area, the open area is transversely provided with a first snap part. The push rod is slidably disposed within the syringe barrel, and an end of the push rod facing the front end part has a second snap part. When the push rod is slidingly moved to the front end part, the second snap part is engaged with the first snap part.

Abstract: A syringe is provided, including a syringe barrel, a needle set and a push rod. A front end part is provided in the syringe barrel. An end of the needle set has an open area, the open area is transversely provided with a first snap part. The push rod is slidably disposed within the syringe barrel, and an end of the push rod facing the front end part has a second snap part. When the push rod is slidingly moved to the front end part, the second snap part is engaged with the first snap part.

Abstract: Disclosure in the description is related to a method for rhythm visualization, a system, and computer-readable storage. The invention allows the system to visualize the rhythm according to audio signals and personal features made by individual. In the method according to one embodiment, a personal image is firstly captured, and features can be extracted from the image. A personalized image is therefore created based on the features. Next, audio features are extracted from the audio signals. A personalized rhythm configuration can be obtained. A personalized rhythm video is therefore created based on the information related to the audio, personalized image, and the personalized rhythm configuration. Furthermore, a group rhythm video may also be obtained as integrating multiple personal rhythm data.

Abstract: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.

Abstract: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.

Abstract: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.

Abstract: Disclosure in the description is related to a method for rhythm visualization, a system, and computer-readable storage. The invention allows the system to visualize the rhythm according to audio signals and personal features made by individual. In the method according to one embodiment, a personal image is firstly captured, and features can be extracted from the image. A personalized image is therefore created based on the features. Next, audio features are extracted from the audio signals. A personalized rhythm configuration can be obtained. A personalized rhythm video is therefore created based on the information related to the audio, personalized image, and the personalized rhythm configuration. Furthermore, a group rhythm video may also be obtained as integrating multiple personal rhythm data.

Abstract: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.

Abstract: A low-offset current-sense amplifier and an operating method thereof are disclosed. The low-offset current-sense amplifier includes a sense amplifier, a first current supply unit, a second current supply unit, and a processing unit. The first current supply unit is coupled to the sense amplifier, and includes a first transistor group and a first current output terminal. The second current supply unit is coupled to the sense amplifier, and includes a second transistor group and a second current output terminal. The processing unit controls the on/off of some transistors of the first transistor group and the second transistor group according to electric currents output from the first current output terminal and the second current output terminal, respectively.

Abstract: A temperature moderation system with temperature difference considerations between indoors and outdoors for facilitating an air conditioner in operation control, includes an indoor unit and an outdoor unit connected with each other. The outdoor unit has an outdoor temperature detection element. The indoor unit has a processor for generating and sending a target temperature to the air conditioner for operation control. The target temperature is one selected from the indoor setting temperature and a pre-set temperature; according to which temperature is closest to the outdoor temperature.

Abstract: Intelligent hotspot connection systems and methods are provided. The intelligent hotspot connection system includes a storage unit, a wireless connection unit, and a processing unit. The storage unit includes a hotspot information database recording at least one property for each of a plurality of hotspots, and a hotspot preference database recording at least one preference inclination, respectively defining a reference weight for the property and signal strength. The processing unit detects the signal strength of the respective hotspots via the wireless connection unit. The processing unit obtains the preference inclination, and calculates a score for the respective hotspots according to the preference inclination, the property and signal strength of the respective hotspots. The processing unit selects and automatically connects to the hotspot with the highest score via the wireless connection unit.

Abstract: A system for product recommendation comprises several automatic service equipments which are mutually linked via a communication network. Each of the automatic service equipments obtains data of other user groups, data of other product groups and other, relation matrixes from other automatic service equipments. Each of the automatic service equipments integrates data of other user groups into data of local user groups stored in itself, and also integrates data of other product groups into data of local product groups stored in itself. Each of the automatic service equipments revises a local relation matrix stored in itself, such that the revised local relation matrix records correlation coefficients between the integrated local user groups and the integrated local product groups. Each of the automatic service equipments performs product recommendation according to the integrated data and input data received through an input device.

Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.

Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.