Abstract: A memory system includes a memory device and a memory controller. The memory controller is configured to in response to an error correction code (ECC) decoding failure for a first read operation, perform a first scan operation corresponding to a target page to obtain a first read offset, the first read offset being an offset that a first read voltage with respect to a first read reference voltage of a first read level. The memory controller is also configured to perform a second scan operation corresponding to the target page to obtain a second read offset. The second read offset is an offset that a second read voltage with respect to a second read reference voltage of a second read level. A scan range of the second scan operation is determined based on an anchor read voltage having a same offset as the first read offset with respect to the second read reference voltage.

Abstract: Examples of the present disclosure provide a memory system and an operation method thereof. The memory system comprises: a memory device and a memory controller coupled to the memory device; wherein, the memory device comprises at least one memory die, and the memory die comprises a plurality of code blocks storing code data; the code data stored in the plurality of code blocks is identical; the memory die comprises a plurality of memory planes, and the plurality of code blocks are stored in different memory planes; the memory controller is configured to: read a portion of code data of each code block of at least a portion of code blocks simultaneously by using an async multi-plane independent reading operation, wherein the read portion of code data of each code block constitutes complete code data stored in one code block.

Abstract: A memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determine an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range can be determined based on the anchor read reference voltage. A second best read offset of a second best read reference voltage with respect to the second read reference voltage can be determined by searching in the first scan range. A reading process can be performed to read the page from the set of MLCs based on the first and second best read reference voltages.

Abstract: The present disclosure provides a memory and an operation method thereof, and a memory system. The memory may include a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array may include a plurality of memory planes. Each of the memory planes may include a plurality of memory pages. The peripheral circuit may be configured to, during performing a read operation in an async multi-plane independent read mode, read a first memory page, and update address information to address information of a memory page next to the first memory page after the read operation on the first memory page. The first memory page may be a first memory page to be read in a currently selected memory plane. The peripheral circuit may be configured to perform sequential cache read on the currently selected memory plane according to the updated address information.

Abstract: An example memory system includes a memory device and a memory controller coupled to the memory device. The memory device may include memory cells having a memory bit count of multiple bits, the memory cells include first and second types of memory bits, the first type of memory bits are used to store valid data, the second type of memory bits are used to store first type of check data, and the first type of check data is obtained by performing error correction encoding on the valid data stored in the first type of memory bits. The memory controller is configured to: perform error correction on the valid data in which an error occurs by at least using the first type of check data in the second type of memory bits when the error occurs in reading the valid data in the first type of memory bits.

Abstract: Examples of the present disclosure provide a memory system and an operation method thereof. The memory system comprises: a memory device and a memory controller coupled to the memory device; wherein, the memory device comprises at least one memory die, and the memory die comprises a plurality of code blocks storing code data; the code data stored in the plurality of code blocks is identical; the memory die comprises a plurality of memory planes, and the plurality of code blocks are stored in different memory planes; the memory controller is configured to: read a portion of code data of each code block of at least a portion of code blocks simultaneously by using an async multi-plane independent reading operation, wherein the read portion of code data of each code block constitutes complete code data stored in one code block.

Abstract: A memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determine an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range can be determined based on the anchor read reference voltage. A second best read offset of a second best read reference voltage with respect to the second read reference voltage can be determined by searching in the first scan range. A reading process can be performed to read the page from the set of MLCs based on the first and second best read reference voltages.

Abstract: Embodiments of the present disclosure disclose a memory system and operation method thereof, a memory controller and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, and m is a positive integer greater than 1. The operation method includes: determining, by the peripheral circuit, (n+1)th group of page data according to a received prefix command and received n groups of page data, wherein n is a positive integer, and n+1 is a positive integer less than or equal to m; and writing the n groups of page data and the (n+1)th group of page data into the memory cell array to generate 2n different data states in the memory cell array.

Abstract: A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

Abstract: An elastic object rendering method and apparatus, a device, and a storage medium are provided. The method comprises: constructing a grid model of an elastic object in response to a deformation trigger operation for the elastic object, first determining the deformation position and speed of an acted point in the grid model of the elastic object under the deformation trigger operation; determining the motion trajectory of each grid point in the grid model of the elastic object according to the deformation position and speed of the acted point, and the elastic constraint of each grid point in the grid model of the elastic object; and finally, according to the motion trajectory of each grid point in the grid model of the elastic object, invoking the grid model of the elastic object to perform elastic motion.

Abstract: A scene controlling method, a device and electronic equipment are provided, which relate to the field of scene controlling. The scene controlling method includes displaying a scene in a first modality, recognizing a trigger object, determining a motion of the trigger object, and switching the scene from the first modality to a second modality based on the motion. The first modality of the scene is associated with the second modality of the scene. Predetermined scene information is retrieved based on the motion of the trigger object so as to switch between scenes or control an element in the scene. By associating the motions of the trigger object with the scenes, the scene displayed on the electronic equipment can be controlled without any hardware upgrade of the conventional electronic equipment, thereby reducing the cost.

Abstract: A scene controlling method, a device and electronic equipment are provided, which relate to the field of scene controlling. The scene controlling method includes displaying a scene in a first modality, recognizing a trigger object, determining a motion of the trigger object, and switching the scene from the first modality to a second modality based on the motion. The first modality of the scene is associated with the second modality of the scene. Predetermined scene information is retrieved based on the motion of the trigger object so as to switch between scenes or control an element in the scene. By associating the motions of the trigger object with the scenes, the scene displayed on the electronic equipment can be controlled without any hardware upgrade of the conventional electronic equipment, thereby reducing the cost.