Abstract: The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.

Abstract: The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.

Abstract: An objective is to provide an information processing device that can be started up stably, and an information processing method. A configuration execution unit of an information processing device writes configuration data into an FPGA. A clock signal monitoring unit detects whether a clock signal supplied from a CPU to the FPGA is stable or not, on condition that a configuration is complete. A startup processing unit starts up the CPU and the FPGA on condition that the clock signal is stable.

Abstract: An objective is to provide an information processing device that can be started up stably, and an information processing method. A configuration execution unit of an information processing device writes configuration data into an FPGA. A clock signal monitoring unit detects whether a clock signal supplied from a CPU to the FPGA is stable or not, on condition that a configuration is complete. A startup processing unit starts up the CPU and the FPGA on condition that the clock signal is stable.

Abstract: A card reader includes a writing coil that is provided to a magnetic head for recording magnetic data in a magnetic card, and a drive circuit that supplies a write current to the writing coil. The drive circuit is a chopping circuit that supplies a chopping current, on/off of which is switched in a specified cycle, as the write current to the writing coil. An on/off cycle of the chopping current is a cycle in which a length of a magnetized pattern in a recording direction is shorter than a reading gap formed in a core around which the writing coil is wound or a core around which a reading coil being separately provided from the writing coil is wound, the magnetized pattern in the recording direction being formed in the magnetic card by the chopping current in a period including one each of the on and the off.

Abstract: A card reader includes a writing coil that is provided to a magnetic head for recording magnetic data in a magnetic card, and a drive circuit that supplies a write current to the writing coil. The drive circuit is a chopping circuit that supplies a chopping current, on/off of which is switched in a specified cycle, as the write current to the writing coil. An on/off cycle of the chopping current is a cycle in which a length of a magnetized pattern in a recording direction is shorter than a reading gap formed in a core around which the writing coil is wound or a core around which a reading coil being separately provided from the writing coil is wound, the magnetized pattern in the recording direction being formed in the magnetic card by the chopping current in a period including one each of the on and the off.

Abstract: A voltage/current reference circuit includes a first bipolar transistor and a second bipolar transistor that exhibit a first voltage drop VBE1 and a second voltage drop VBE2, respectively. A first resistor, having a resistance R1, is configured to draw a first current equal to (VBE1?VBE2)/R1. A second resistor, having a resistance R2, is configured to draw a second current equal to VBE1/R2. A first transistor supplies the first and second currents to the first and second resistors. A second transistor, having a current mirror configuration with respect to the first transistor, directly provides a reference current equal to (VBE1?VBE2)/R1+VBE1/R2. A third transistor, having a current mirror configuration with respect to the first transistor, provides a current equal to the reference current to a third resistor having a resistance R3 and a third bipolar transistor that exhibits a third voltage drop VBE3, thereby generating a reference voltage.

Abstract: A voltage/current reference circuit includes a first bipolar transistor and a second bipolar transistor that exhibit a first voltage drop VBE1 and a second voltage drop VBE2, respectively. A first resistor, having a resistance R1, is configured to draw a first current equal to (VBE1?VBE2)/R1. A second resistor, having a resistance R2, is configured to draw a second current equal to VBE1/R2. A first transistor supplies the first and second currents to the first and second resistors. A second transistor, having a current mirror configuration with respect to the first transistor, directly provides a reference current equal to (VBE1?VBE2)/R1+VBE1/R2. A third transistor, having a current mirror configuration with respect to the first transistor, provides a current equal to the reference current to a third resistor having a resistance R3 and a third bipolar transistor that exhibits a third voltage drop VBE3, thereby generating a reference voltage.