Abstract: The present invention belongs to the technical field of green catalysis and biosynthesis, and particularly relates to a carbon-based microreactor, and a preparation method and application thereof. According to the present invention, a carbon-based microchannel monolithic column is prepared by utilizing a graded pore structure of regular channels of natural wood in combination with an inorganic salt supporting framework, temperature programmed accurate carbonization and other methods, and then, the multiple advantages of the carbon monolithic column, the microreactor, and immobilized enzyme/chemical catalyst are fully played from the view of key technologies such as carbon-based microreactor construction, operation control, etc.

Abstract: A levitating object includes a housing and a magnetic member. The housing and the magnetic member are configured to be relatively movable, and the relative movement between the magnetic member and the housing are guided through a linear guide mechanism provided in the levitating object. According to the present disclosure, a magnetic member capable of linearly moving or vertically moving is provided in the levitating object, so that self-lifting and lowering levitation or landing of the levitating object relative to a levitator base can be easily achieved without providing a lifting and lowering mechanism in the levitator base. In this way, an extremely strong visual special effect and a sense of magic are achieved, and the levitator base can still maintain an original compact or miniaturized flat structure.

Abstract: A method of storing data in general purpose registers (GPRs) includes packing a tile of data items into GPRs, where the tile includes multiple channels. The tile of data items is read from memory. At least two channels of the data are stored in a first GPR, and at least two additional channels are stored in a second GPR. Auxiliary data is loaded into a third GPR. The auxiliary data and the tile data can be used together for performing convolution operations.

Abstract: A method for computing, a computing device, and a computer-readable storage medium are provided. The method includes determining a first pixel block in a cache. The first pixel block is composed of a 2m row×2n column pixel matrix and includes original pixel data and pixel data related to the original pixel data. The first pixel block is read from the cache. At least part of the pixel data related to the original pixel data is used for padding related to the original pixel data. The original pixel data includes pixel data from the (n+1)th column to the 2nth column in the (m+1)th row to the 2mth row in the 2m row×2 n column pixel matrix. When reading data from the cache, pixel data that needs to be obtained after insert-zero and padding operations on the original pixel data in back propagation can be read at one time.

Abstract: A self-decoupling wideband antenna system and a terminal device, including: a first end of a first radiation stub that is connected to a first ground point, and the first radiation stub is further connected to a first feed point; a first end of a second radiation stub and a first end of a third radiation stub are connected to a second ground point, and a slot is provided between a second end of the second radiation stub and a second end of the first radiation stub. A distance between the second end of the second radiation stub and the second end of the first radiation stub is less than a distance between the first end of the second radiation stub and the second end of the first radiation stub.

Abstract: An information processing method, an interconnection device, and a computer-readable storage medium are provided. The interconnection device includes a request processing module configured for: receiving a data access request from at least one processor, wherein the data access request comprises a merge bit, a multicast group identifier (MGID), and a multicast transaction identifier (MTID); determining whether the data access request is a multicast request; determining whether the interconnection device receives other multicast requests if it is determined that the data access request is a multicast request based on the MGID, the MTID, and a static routing policy of a multicast group; and obtaining the other multicast requests if it is determined that the interconnection device receives the other multicast requests, merging the multicast request with the other multicast requests into a merged request, and forwarding the merged request to a next-hop device of the interconnection device.

Abstract: The present disclosure relates to a method for computing, computing device and computer-readable storage medium. The method includes: determining a pixel block set in a cache, a first pixel block in the pixel block set comprising an m×n pixel matrix having a first padding setting related to the original pixel data, the m and n being positive integers; and storing the determined pixel block set in a buffer to enable a second pixel block to be read from the buffer based on the buffer initial address of the first pixel block and an address offset associated with the second pixel block, wherein the second pixel block has a second padding setting related to the original pixel data, and the first padding setting and the second padding setting have the same offset amount in a first direction relative to the original pixel data.

Abstract: The disclosed technology relates to graphics processing units (GPU), In one aspect, a GPU includes a general purpose register (GPR) including registers, an arithmetic logic unit (ALU) reading pixels of an image independently of a shared memory, and a level 1 (L1) cache storing pixels to implement a pixel mapping that maps the pixels read from the L1 cache into the registers of the GPR. The pixel mapping includes separating pixels of an image into three regions, with each region including a set of pixels. A first and second set of the pixels are loaded into registers corresponding to two of the three regions horizontally, and a third set of the pixels are loaded into registers corresponding to the third of the three regions vertically. Each of the registers in the first, second, and third registers are loaded as a contiguous ordered number of registers in the GPR.

Abstract: A system. The system includes an image display system, a display device, a camera system, one or more control devices and a control system. The display device is configured to display an image received from the image display system. The camera system is configured to capture the image displayed by the display device during a capture of a scene. The control system is communicably coupled to the image display system, the display device, the camera system and the one or more control devices. The control system comprises a processing circuit and is configured to automatically adjust settings of the image display system, the display device and the camera system. The control system is also configured to determine which of the adjustments results in the least destruction to the image, and apply the adjustment which results in the least destruction to the image.

Abstract: The disclosed technology generally relates to a graphics processing unit (GPU). In one aspect, a GPU includes a general purpose register (GPR) having registers, an arithmetic logic unit (ALU) configured to read pixels of an image independently of a shared memory, and a level 1 (L1) cache storing the pixels read by the ALU. The ALU can implement pixel mapping by fetching a quad of pixels, which includes pixels of first, second, third, and fourth pixel types, from the L1 cache, grouping the pixels of the different pixel types of the quad into four groups based on pixel type, and, for each group, separating the pixels included in the group into three regions that each have a set of pixels. The pixels for each group can then be loaded into the registers corresponding to the three regions.

Abstract: Methodologies and architectures are provided for inter-thread sharing of data in a general purpose register (GPR) of a multiprocessor apparatus. The data sharing is performed by a graphics processing unit (GPU) having at least one processing cluster including a plurality of processing cores (PCs) configured for parallel operation. Each PC of a cluster is configured to utilize a dedicated portion of the GPR. The GPU further includes a shared memory for the cluster, and a memory read/write hub coupled to the GPR and shared memory, the hub including a crossbar switch. A PC executes a move data instruction, including operands referencing a destination portion of the GPR and a source portion assigned to the PC, to retrieve data from the source portion. The memory read/write hub writes the data, via the crossbar switch, to the destination portion of the GPR without first writing the data to the shared memory.

Abstract: The embodiments of the disclosure relate to a computing device, a computing equipment, and a programmable scheduling method for data loading and execution, and relate to the field of computer. The computing device is coupled to a first computing core and a first memory. The computing device includes a scratchpad memory, a second computing core, a first hardware queue, a second hardware queue and a synchronization unit. The second computing core is configured for acceleration in a specific field. The first hardware queue receives a load request from the first computing core. The second hardware queue receives an execution request from the first computing core. The synchronization unit configured to make the triggering of the load request and the execution request to cooperate with each other. In this manner, flexibility, throughput, and overall performance can be enhanced.

Abstract: An information processing method, an interconnection device, and a computer-readable storage medium are provided. The interconnection device includes a request processing module configured for: receiving a data access request from at least one processor, wherein the data access request comprises a merge bit, a multicast group identifier (MGID), and a multicast transaction identifier (MTID); determining whether the data access request is a multicast request; determining whether the interconnection device receives other multicast requests if it is determined that the data access request is a multicast request based on the MGID, the MTID, and a static routing policy of a multicast group; and obtaining the other multicast requests if it is determined that the interconnection device receives the other multicast requests, merging the multicast request with the other multicast requests into a merged request, and forwarding the merged request to a next-hop device of the interconnection device.

Abstract: An information processing method, an interconnection device, and a computer-readable storage medium are provided. The interconnection device includes a request processing module configured for: receiving a data access request from at least one processor, wherein the data access request comprises a merge bit, a multicast group identifier (MGID), and a multicast transaction identifier (MTID); determining whether the data access request is a multicast request; determining whether the interconnection device receives other multicast requests if it is determined that the data access request is a multicast request based on the MGID, the MTID, and a static routing policy of a multicast group; and obtaining the other multicast requests if it is determined that the interconnection device receives the other multicast requests, merging the multicast request with the other multicast requests into a merged request, and forwarding the merged request to a next-hop device of the interconnection device.

Abstract: The invention relates to an apparatus for vector computing incorporating with matrix multiply and accumulation (MMA) calculation. The apparatus includes a streaming multiprocessor (SM), and a block selector. The register space is divided into physical blocks, each of which includes register groups, and a general matrix multiply (GEMM) calculation unit. The SM includes a general-purpose register (GPR), and the GEMM calculation unit includes an instruction queue and a arithmetic logical unit (ALU). The ALU coupled to the GPR is arranged operably to perform MMA calculation according to a GEMM instruction stored in the instruction queue, and store a calculation result in the GPR.

Abstract: A method for acquiring push information can be applied to a terminal device and include: transmitting a device model of the terminal device to a server; receiving a push software development kit corresponding to the device model, and a configuration file corresponding to the push software development kit transmitted by the server; initializing the push software development kit based on the configuration file, and completing a registration with the server; and receiving, through the push software development kit, push information transmitted by the server. The terminal device can therefore acquire its corresponding push software development kit according to the device model of the terminal device through a plug-in method, thereby increase push arrival rate and improve quality of operational data.

Abstract: The embodiments of the disclosure relate to a computing device and a method for loading data. According to the method, the first processing unit sends a first instruction to the NMP unit. The first instruction includes a first address, a plurality of second addresses, and an operation type. In response to the first instruction, the NMP unit performs operations associated with the operation type on multiple data items on the multiple second addresses of the first memory, so as to generate the operation result. The NMP unit stores the operation result to the first address of the first memory. The first processing unit issues a flush instruction to make the operation result on the first address visible to the first processing unit. The first processing unit issues a read instruction to read the operation result on the first address to the first processing unit.

Abstract: A system. The system includes an image display system, a display device, a camera system, one or more control devices and a control system. The display device is configured to display an image received from the image display system. The camera system is configured to capture the image displayed by the display device during a capture of a scene. The control system is communicably coupled to the image display system, the display device, the camera system and the one or more control devices. The control system comprises a processing circuit and is configured to automatically adjust settings of the image display system, the display device and the camera system. The control system is also configured to determine which of the adjustments results in the least destruction to the image, and apply the adjustment which results in the least destruction to the image.

Abstract: A method for computing, a computing device, and a computer-readable storage medium are provided. The method includes determining a first pixel block in a cache. The first pixel block is composed of a 2m row×2n column pixel matrix and includes original pixel data and pixel data related to the original pixel data. The first pixel block is read from the cache. At least part of the pixel data related to the original pixel data is used for padding related to the original pixel data. The original pixel data includes pixel data from the (n+1)th column to the 2nth column in the (m+1)th row to the 2mth row in the 2m row×2 n column pixel matrix. When reading data from the cache, pixel data that needs to be obtained after insert-zero and padding operations on the original pixel data in back propagation can be read at one time.

Abstract: Embodiments of the present disclosure relate to a method for data processing and to the field of computers. The method comprises: in the mth clock cycle, determining a first exponent value; in the m+1th clock cycle, inputting two n-dimensional vectors into the processing unit to determine n second exponent values; determining a maximum value among the first exponent value and the determined n second exponent values; determining whether a target second exponent value exists among the n second exponent values, an absolute value of a difference between the target second exponent value and the maximum value being greater than or equal to a first threshold; and in response to determining that the target second exponent value exists in n second exponent values, not performing a multiply operation of two floating point numbers corresponding to the target second exponent value in the processing unit, during the m+1th clock cycle.