Patents by Inventor Yufeng Guo

Yufeng Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12375039
    Abstract: Disclosed in the present invention is a crystal oscillator based on duty ratio measurement, comprising a first inverter, a resistor, a first load capacitor, a second load capacitor, first to fourth switches, a quartz crystal, a buffer, a sampling and holding module, a first comparator, a second comparator, a phase conversion module, a digital control module, and an energy injection module. One end of the quartz crystal is used for signal injection, a signal at the other end of the quartz crystal is sampled and processed, information representing phase error accumulation, i.e., a signal of which the duty ratio is continuously changing, is obtained by means of the first comparator, and finally the duty ratio is measured by means of the phase conversion module and the second comparator, so as to obtain an accurate moment of phase switching.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: July 29, 2025
    Assignees: Nanjing University Of Posts And Telecommunications, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD.
    Inventors: Zixuan Wang, Xin Wang, Zhikuang Cai, Yufeng Guo, Jiafei Yao
  • Publication number: 20250219578
    Abstract: Disclosed in the present invention is a crystal oscillator based on duty ratio measurement, comprising a first inverter, a resistor, a first load capacitor, a second load capacitor, first to fourth switches, a quartz crystal, a buffer, a sampling and holding module, a first comparator, a second comparator, a phase conversion module, a digital control module, and an energy injection module. One end of the quartz crystal is used for signal injection, a signal at the other end of the quartz crystal is sampled and processed, information representing phase error accumulation, i.e., a signal of which the duty ratio is continuously changing, is obtained by means of the first comparator, and finally the duty ratio is measured by means of the phase conversion module and the second comparator, so as to obtain an accurate moment of phase switching.
    Type: Application
    Filed: May 11, 2023
    Publication date: July 3, 2025
    Applicants: Nanjing University Of Posts And Telecommunications, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD.
    Inventors: Zixuan WANG, Xin WANG, Zhikuang CAI, Yufeng GUO, Jiafei YAO
  • Patent number: 12332126
    Abstract: A low-power-consumption low-voltage digital temperature sensor, which acquires temperature information by means of the frequency ratio of a first oscillation signal outputted by a first annular oscillator to a second oscillation signal outputted by a second annular oscillator. The first annular oscillator additionally uses an MOS varactor as a load capacitor, and uses the voltage characteristics of the MOS varactor to lower the power supply voltage fluctuation sensitivity, which is suitable for a low-power-consumption low-voltage environment; meanwhile, the sensor has the advantages of a small size, high digitization, self referencing and the like.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: June 17, 2025
    Assignee: Nanjing University Of Post And Telecommunications
    Inventors: Zhikuang Cai, Zixuan Wang, Chen Li, Zushuai Xie, Jingjing Guo, Lu Liu, Yufeng Guo
  • Patent number: 12302425
    Abstract: A wireless communication method includes after a master device establishes a wireless connection to a slave device, performing negotiation on sound effect processing The master device determines, based on indication information fed back by the slave device, whether joint sound effect processing can be performed between the master device and the slave device. If joint sound effect processing can be performed, the method includes performing adaptive sound effect processing on both master device and slave device sides.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: May 13, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yufeng Guo, Wei Qin
  • Patent number: 12265123
    Abstract: A universal test chiplet for testing a plurality of chiplets to be tested is provided. The universal test chiplet includes a chiplet test control circuit module, a test data distribution circuit module, a memory test configuration circuit module, and a chiplet test interface circuit module. The chiplet test control circuit module is configured to provide test data and configure test modes for the chiplets to be tested. The test data distribution circuit module is configured to distribute the test data required by each of the chiplets to be tested from a test data bus. The memory test configuration circuit module is configured to provide test circuits for memories of the chiplets to be tested and automatically generate a test vector. The chiplet test interface circuit module is configured to transmit the test data to the chiplets to be tested in any direction through chiplet test interfaces.
    Type: Grant
    Filed: September 29, 2024
    Date of Patent: April 1, 2025
    Assignees: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD.
    Inventors: Zhikuang Cai, Xiaoting Liu, Luping Zhang, Zixuan Wang, Dapeng Yan, Binbin Xu, Haiyan Sun, Lu Liu, Yufeng Guo
  • Patent number: 12235996
    Abstract: A security architecture system includes a plurality of subsystems. The plurality of subsystems include a secure element subsystem. A first subsystem of the plurality of subsystems includes a trusted computing platform that has a trusted platform control module. The first subsystem is configured to, for a running object in one or more subsystems other than the first subsystem in the plurality of subsystems, use the trusted platform control module to perform security measurement on the running object based on a measurement strategy and a measurement benchmark value to obtain a measurement result. The measurement result is used to control a running state of the running object in one or more subsystems other than the first subsystem in the plurality of subsystems.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: February 25, 2025
    Assignee: PHYTIUM TECHNOLOGY CO., LTD.
    Inventors: Qiang Dou, Yufeng Guo, Yanzhao Feng, Ming Zhang, Zhuo Ma
  • Patent number: 12188984
    Abstract: A circuit for post-binding testing of a 2.5D chiplet includes an interposer-dedicated TAP controller, an interposer test interface circuit and a chiplet test output control circuit. A chiplet test configuration register and its corresponding instructions are newly added for the interposer-dedicated TAP controller. The interposer test interface circuit uses an output control signal of the chiplet test configuration register to select the opening or closing of a test signal channel between an interposer and a chiplet. The chiplet test output control circuit uses the chiplet test configuration register to output a control signal for control of a test data output of the chiplet on the interposer.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: January 7, 2025
    Assignees: Nanjing University Of Posts And Telecommunications, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD.
    Inventors: Zhikuang Cai, Guopeng Zhou, Haijun Shen, Binbin Xu, Jiafei Yao, Henglu Wang, Zushuai Xie, Jian Xiao, Zixuan Wang, Yufeng Guo
  • Publication number: 20250006289
    Abstract: A reconfigurable MBIST method based on an adaptive March algorithm is provided. The reconfigurable MBIST method automatically reconfigures different algorithm circuits according to external environment and user instructions to satisfy detection requirements for different faults. The provided adaptive March algorithm is capable of adaptively reorganizing algorithms with different complexities, such that dynamic adjustments can be executed between time complexities of the algorithm and fault coverage rates to achieve a good balance, and the static fault coverage rates are high, thereby effectively improving dynamic fault coverage rates.
    Type: Application
    Filed: January 10, 2023
    Publication date: January 2, 2025
    Applicants: Nanjing University Of Posts And Telecommunications, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD.
    Inventors: Zhikuang CAI, Haojie YU, Haijun SHEN, Zushuai XIE, Jingjing GUO, Lu LIU, Jiafei YAO, Henglu WANG, Zixuan WANG, Jian XIAO, Yufeng GUO
  • Publication number: 20240369631
    Abstract: Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.
    Type: Application
    Filed: June 20, 2022
    Publication date: November 7, 2024
    Applicants: Nanjing University Of Posts And Telecommunications, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO.,LTD.
    Inventors: Zhikuang CAI, Yunbo WANG, Jian SONG, Guopeng ZHOU, Jiafei YAO, Binbin XU, Henglu WANG, Zixuan WANG, Yufeng GUO
  • Patent number: 12135354
    Abstract: Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: November 5, 2024
    Assignees: Nanjing University Of Posts And Telecommunications, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD.
    Inventors: Zhikuang Cai, Yunbo Wang, Jian Song, Guopeng Zhou, Jiafei Yao, Binbin Xu, Henglu Wang, Zixuan Wang, Yufeng Guo
  • Patent number: 12099086
    Abstract: The present disclosure relates to the field of design for testability of super-large-scale integrated circuits, and discloses a flexible configurable module (FCM) based chiplet test circuit. The core structure of the circuit is located at an interposer. The test circuit includes FCMs, a control signal configuration module and a test state control module, where the FCM adopts a two-way skew-symmetric structure to implement data transmission in the horizontal direction and the vertical direction; the control signal configuration module is connected to control signals of all the FCMs, so as to control the data transmission directions as well as switch on and switch off states of all the FCMs; and the test state control module controls the shift and update operations of data inside the FCMs and the control signal configuration module.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: September 24, 2024
    Assignees: Nanjing University of Posts and Telecommunications, Nantong Institute of Nanjing University of Posts and Telecommunications Co., Ltd.
    Inventors: Zhikuang Cai, Jian Song, Guopeng Zhou, Zushuai Xie, Henglu Wang, Binbin Xu, Jiafei Yao, Zixuan Wang, Yufeng Guo
  • Publication number: 20240310220
    Abstract: A low-power-consumption low-voltage digital temperature sensor, which acquires temperature information by means of the frequency ratio of a first oscillation signal outputted by a first annular oscillator to a second oscillation signal outputted by a second annular oscillator. The first annular oscillator additionally uses an MOS varactor as a load capacitor, and uses the voltage characteristics of the MOS varactor to lower the power supply voltage fluctuation sensitivity, which is suitable for a low-power-consumption low-voltage environment; meanwhile, the sensor has the advantages of a small size, high digitization, self referencing and the like.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 19, 2024
    Inventors: Zhikuang CAI, Zixuan WANG, Chen LI, Zushuai XIE, Jingjing GUO, Lu LIU, Yufeng GUO
  • Patent number: 12093633
    Abstract: The present disclosure discloses a method for extracting parasitic capacitance of interconnection lines of an integrated circuit based on discontinuous Galerkin finite element method.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: September 17, 2024
    Assignees: Nanjing University Of Posts And Telecommunications, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD.
    Inventors: Zhikuang Cai, Hang Yang, Zhenghao Zhao, Hongqiang Zhu, Henglu Wang, Jingjing Guo, Jiafei Yao, Yufeng Guo
  • Publication number: 20240289531
    Abstract: The present disclosure discloses a method for extracting parasitic capacitance of interconnection lines of an integrated circuit based on discontinuous Galerkin finite element method.
    Type: Application
    Filed: May 27, 2022
    Publication date: August 29, 2024
    Applicants: Nanjing University Of Posts And Telecommunications, NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO.,LTD.
    Inventors: Zhikuang CAI, Hang YANG, Zhenghao ZHAO, Hongqiang ZHU, Henglu WANG, Jingjing GUO, Jiafei YAO, Yufeng GUO
  • Publication number: 20240288492
    Abstract: The present disclosure relates to the field of design for testability of super-large-scale integrated circuits, and discloses a flexible configurable module (FCM) based chiplet test circuit. The core structure of the circuit is located at an interposer. The test circuit includes FCMs, a control signal configuration module and a test state control module, where the FCM adopts a two-way skew-symmetric structure to implement data transmission in the horizontal direction and the vertical direction; the control signal configuration module is connected to control signals of all the FCMs, so as to control the data transmission directions as well as switch on and switch off states of all the FCMs; and the test state control module controls the shift and update operations of data inside the FCMs and the control signal configuration module.
    Type: Application
    Filed: October 20, 2022
    Publication date: August 29, 2024
    Applicants: Nanjing University of Posts and Telecommunications, Nantong Institute of Nanjing University of Posts and Telecommunications Co.,Ltd.
    Inventors: Zhikuang CAI, Jian SONG, Guopeng ZHOU, Zushuai XIE, Henglu WANG, Binbin XU, Jiafei YAO, Zixuan WANG, Yufeng GUO
  • Publication number: 20230209624
    Abstract: A wireless communication method includes after a master device establishes a wireless connection to a slave device, performing negotiation on sound effect processing. The master device determines, based on indication information fed back by the slave device, whether joint sound effect processing can be performed between the master device and the slave device. If joint sound effect processing can be performed, the method includes performing adaptive sound effect processing on both master device and slave device sides.
    Type: Application
    Filed: May 20, 2021
    Publication date: June 29, 2023
    Inventors: Yufeng Guo, Wei Qin
  • Publication number: 20230177196
    Abstract: A resource management method suitable for a security architecture system including a secure element subsystem. The security architecture system is configured with N chip lifecycle states, N being an integer greater than 1, the secure element subsystem stores a plurality of resources, an access authority of the resources being associated with the N chip lifecycle states. The method includes performing access control on a resource based on a current chip lifecycle state of the security architecture system, the current chip lifecycle state of the security architecture system belonging to one of the N chip lifecycle states.
    Type: Application
    Filed: November 21, 2022
    Publication date: June 8, 2023
    Inventors: Ming ZHANG, Yanzhao FENG, Yufeng GUO, Qingshan ZHU, Zhuo MA, Zhiqiang CHEN, Jianyue WANG
  • Patent number: 11609323
    Abstract: An ultra-wideband ground penetrating radar control system, comprising a synchronous clock generating circuit, a GPS positioning module, a measuring wheel encoder module, a digitally controlled delay circuit for equivalent sampling, an analog-to-digital conversion (ADC) circuit, and a main controller. The synchronous clock generating circuit, the GPS positioning module, the measuring wheel encoder module, the digitally controlled delay circuit and the ADC circuit are all connected to the main controller. The synchronous clock generating circuit is further connected to an external ultra-wideband radar transmitter. The digitally controlled delay circuit is further connected to an external sampling pulse generation circuit for equivalent sampling. The ADC circuit is further connected to an external sampling gate for equivalent sampling. The main controller is further connected to an external server via Ethernet. The volume of an ultra-wideband ground penetrating radar control system is reduced.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: March 21, 2023
    Assignee: Nantong Institute of Nanjing University of Posts and Telecommunications Co., Ltd.
    Inventors: Zhikuang Cai, Xuanchen Qi, Wenhua Lin, Ji Wang, Jian Xiao, Yufeng Guo
  • Publication number: 20230069047
    Abstract: A microprocessor comprising a cryptographic engine and a controller. The controller is connected to the cryptographic engine and configured to receive a plurality of access requests from a plurality of execution environments, respectively and respond to one of the plurality of access requests and instruct the cryptographic engine to execute a cryptographic algorithm.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 2, 2023
    Inventors: Yanzhao FENG, Qiang DOU, Yufeng GUO, Ming ZHANG, Zhuo MA, Qiaoqiao HU, Yongpeng LIU
  • Publication number: 20230068658
    Abstract: A microprocessor includes a cryptographic engine and a controller. The cryptographic engine is configured to execute a cryptographic algorithm. The controller is connected to the cryptographic engine. The controller is configured to receive an access request from a first execution environment. The access request accesses the cryptographic engine to execute the cryptographic algorithm. The access request includes at least identification information. The identification information indicates that the access request is from the first execution environment. The first execution environment is an execution environment of a number N execution environments. N is an integer greater than or equal to 1. The controller is further configured to, based on the identification information, instruct the cryptographic engine to execute the cryptographic algorithm that needs to be executed required by the access request.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 2, 2023
    Inventors: Qiang DOU, Yanzhao FENG, Yufeng GUO, Ming ZHANG, Zhuo MA, Qingshan ZHU, Zhiqiang CHEN