Abstract: A universal test chiplet for testing a plurality of chiplets to be tested is provided. The universal test chiplet includes a chiplet test control circuit module, a test data distribution circuit module, a memory test configuration circuit module, and a chiplet test interface circuit module. The chiplet test control circuit module is configured to provide test data and configure test modes for the chiplets to be tested. The test data distribution circuit module is configured to distribute the test data required by each of the chiplets to be tested from a test data bus. The memory test configuration circuit module is configured to provide test circuits for memories of the chiplets to be tested and automatically generate a test vector. The chiplet test interface circuit module is configured to transmit the test data to the chiplets to be tested in any direction through chiplet test interfaces.

Abstract: A security architecture system includes a plurality of subsystems. The plurality of subsystems include a secure element subsystem. A first subsystem of the plurality of subsystems includes a trusted computing platform that has a trusted platform control module. The first subsystem is configured to, for a running object in one or more subsystems other than the first subsystem in the plurality of subsystems, use the trusted platform control module to perform security measurement on the running object based on a measurement strategy and a measurement benchmark value to obtain a measurement result. The measurement result is used to control a running state of the running object in one or more subsystems other than the first subsystem in the plurality of subsystems.

Abstract: A circuit for post-binding testing of a 2.5D chiplet includes an interposer-dedicated TAP controller, an interposer test interface circuit and a chiplet test output control circuit. A chiplet test configuration register and its corresponding instructions are newly added for the interposer-dedicated TAP controller. The interposer test interface circuit uses an output control signal of the chiplet test configuration register to select the opening or closing of a test signal channel between an interposer and a chiplet. The chiplet test output control circuit uses the chiplet test configuration register to output a control signal for control of a test data output of the chiplet on the interposer.

Abstract: A reconfigurable MBIST method based on an adaptive March algorithm is provided. The reconfigurable MBIST method automatically reconfigures different algorithm circuits according to external environment and user instructions to satisfy detection requirements for different faults. The provided adaptive March algorithm is capable of adaptively reorganizing algorithms with different complexities, such that dynamic adjustments can be executed between time complexities of the algorithm and fault coverage rates to achieve a good balance, and the static fault coverage rates are high, thereby effectively improving dynamic fault coverage rates.

Abstract: Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.

Abstract: Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.

Abstract: The present disclosure relates to the field of design for testability of super-large-scale integrated circuits, and discloses a flexible configurable module (FCM) based chiplet test circuit. The core structure of the circuit is located at an interposer. The test circuit includes FCMs, a control signal configuration module and a test state control module, where the FCM adopts a two-way skew-symmetric structure to implement data transmission in the horizontal direction and the vertical direction; the control signal configuration module is connected to control signals of all the FCMs, so as to control the data transmission directions as well as switch on and switch off states of all the FCMs; and the test state control module controls the shift and update operations of data inside the FCMs and the control signal configuration module.

Abstract: A low-power-consumption low-voltage digital temperature sensor, which acquires temperature information by means of the frequency ratio of a first oscillation signal outputted by a first annular oscillator to a second oscillation signal outputted by a second annular oscillator. The first annular oscillator additionally uses an MOS varactor as a load capacitor, and uses the voltage characteristics of the MOS varactor to lower the power supply voltage fluctuation sensitivity, which is suitable for a low-power-consumption low-voltage environment; meanwhile, the sensor has the advantages of a small size, high digitization, self referencing and the like.

Abstract: The present disclosure discloses a method for extracting parasitic capacitance of interconnection lines of an integrated circuit based on discontinuous Galerkin finite element method.

Abstract: The present disclosure relates to the field of design for testability of super-large-scale integrated circuits, and discloses a flexible configurable module (FCM) based chiplet test circuit. The core structure of the circuit is located at an interposer. The test circuit includes FCMs, a control signal configuration module and a test state control module, where the FCM adopts a two-way skew-symmetric structure to implement data transmission in the horizontal direction and the vertical direction; the control signal configuration module is connected to control signals of all the FCMs, so as to control the data transmission directions as well as switch on and switch off states of all the FCMs; and the test state control module controls the shift and update operations of data inside the FCMs and the control signal configuration module.

Abstract: The present disclosure discloses a method for extracting parasitic capacitance of interconnection lines of an integrated circuit based on discontinuous Galerkin finite element method.

Abstract: A wireless communication method includes after a master device establishes a wireless connection to a slave device, performing negotiation on sound effect processing. The master device determines, based on indication information fed back by the slave device, whether joint sound effect processing can be performed between the master device and the slave device. If joint sound effect processing can be performed, the method includes performing adaptive sound effect processing on both master device and slave device sides.

Abstract: A resource management method suitable for a security architecture system including a secure element subsystem. The security architecture system is configured with N chip lifecycle states, N being an integer greater than 1, the secure element subsystem stores a plurality of resources, an access authority of the resources being associated with the N chip lifecycle states. The method includes performing access control on a resource based on a current chip lifecycle state of the security architecture system, the current chip lifecycle state of the security architecture system belonging to one of the N chip lifecycle states.

Abstract: An ultra-wideband ground penetrating radar control system, comprising a synchronous clock generating circuit, a GPS positioning module, a measuring wheel encoder module, a digitally controlled delay circuit for equivalent sampling, an analog-to-digital conversion (ADC) circuit, and a main controller. The synchronous clock generating circuit, the GPS positioning module, the measuring wheel encoder module, the digitally controlled delay circuit and the ADC circuit are all connected to the main controller. The synchronous clock generating circuit is further connected to an external ultra-wideband radar transmitter. The digitally controlled delay circuit is further connected to an external sampling pulse generation circuit for equivalent sampling. The ADC circuit is further connected to an external sampling gate for equivalent sampling. The main controller is further connected to an external server via Ethernet. The volume of an ultra-wideband ground penetrating radar control system is reduced.

Abstract: A microprocessor comprising a cryptographic engine and a controller. The controller is connected to the cryptographic engine and configured to receive a plurality of access requests from a plurality of execution environments, respectively and respond to one of the plurality of access requests and instruct the cryptographic engine to execute a cryptographic algorithm.

Abstract: A microprocessor includes a cryptographic engine and a controller. The cryptographic engine is configured to execute a cryptographic algorithm. The controller is connected to the cryptographic engine. The controller is configured to receive an access request from a first execution environment. The access request accesses the cryptographic engine to execute the cryptographic algorithm. The access request includes at least identification information. The identification information indicates that the access request is from the first execution environment. The first execution environment is an execution environment of a number N execution environments. N is an integer greater than or equal to 1. The controller is further configured to, based on the identification information, instruct the cryptographic engine to execute the cryptographic algorithm that needs to be executed required by the access request.

Abstract: A microprocessor includes a cryptographic engine, M buffer units, and a controller. The cryptographic engine is configured to execute cryptographic algorithms. The M buffer units are configured to cache data required by an access request of a corresponding execution environment. M is an integer greater than or equal to 1. The controller is connected to the cryptographic engine and the M buffer units. The controller is configured to receive the access request from a first execution environment and instruct the cryptographic engine to execute the cryptographic algorithm requested by the access request using the required data cached by the buffer unit corresponding to the first execution environment from which the access request comes. The access request is used to access the cryptographic engine to execute a cryptographic algorithm. The first execution environment is one execution environment among N execution environments. N is an integer greater than or equal to 1.

Abstract: A method for preventing a differential cryptanalysis attack is provided. The method is implemented by an adaptive scan chain, a control module, and a plaintext analysis module. The plaintext analysis module controls the adaptive scan chain, so that two plaintexts differing in the last bit of only one byte are input through scan chains with different structures. Consequently, the two input plaintexts for which differential cryptanalysis attack technology originally can be used to crack the key are unable to generate outputs that can be used by the differential cryptanalysis attack technology.

Abstract: A method for preventing a differential cryptanalysis attack is provided. The method is implemented by an adaptive scan chain, a control module, and a plaintext analysis module. The plaintext analysis module controls the adaptive scan chain, so that two plaintexts differing in the last bit of only one byte are input through scan chains with different structures. Consequently, the two input plaintexts for which differential cryptanalysis attack technology originally can be used to crack the key are unable to generate outputs that can be used by the differential cryptanalysis attack technology.

Abstract: A server receives article information of an article to be estimated from a user. The server obtains an actual picture of the article from the user. The server determines a standard picture of the article from a predetermined graphics library based on the article information. The server obtains an actual performance of the article. The server determines a value of the article based on the standard picture, the actual picture, and the actual performance of the article.