Patents by Inventor Yugi Morimoto

Yugi Morimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads
    Patent number: 9734033
    Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
  • Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads
    Patent number: 9720793
    Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
  • IMPLEMENTING PROCESSOR FUNCTIONAL VERIFICATION BY GENERATING AND RUNNING CONSTRAINED RANDOM IRRITATOR TESTS FOR MULTIPLE PROCESSOR SYSTEM AND PROCESSOR CORE WITH MULTIPLE THREADS
    Publication number: 20160162380
    Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 9, 2016
    Inventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
  • IMPLEMENTING PROCESSOR FUNCTIONAL VERIFICATION BY GENERATING AND RUNNING CONSTRAINED RANDOM IRRITATOR TESTS FOR MULTIPLE PROCESSOR SYSTEM AND PROCESSOR CORE WITH MULTIPLE THREADS
    Publication number: 20160162381
    Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.
    Type: Application
    Filed: September 20, 2015
    Publication date: June 9, 2016
    Inventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
  • VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE
    Publication number: 20110320784
    Abstract: A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initialization of instruction code into the SMC trap source.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eli Almog, Christopher A. Krygowski, Yugi Morimoto, Michal Rimon