Abstract: A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film between the floating and the control gate electrode; a pair of select gate transistors on the semiconductor substrate with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode; a polyplug of the first thickness situated between the second gate electrodes of the pair of select gate transistors; and a metal plug provided on the polyplug.

Abstract: A semiconductor device includes a first insulating film, paired resistance elements each of which includes a first conductive film formed on the first insulating film, a second insulating film formed on the first conductive film and a second conductive film formed on the second insulating film, paired first contact plugs formed on one of the resistance elements and arranged along a first direction, and paired second contact plugs formed on the other resistance. One of the resistance elements has a first width in a second direction perpendicular to the first direction, and a semiconductor region surrounded by an element isolation region has a second width. The first width is smaller than half of the second width. The second insulating films are spaced from each other by a first distance. The second conductive films are spaced from each other by a second distance. The second distance is longer than the first distance.

Abstract: According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device including: sequentially forming a first insulating film, a first electrode film, a second insulating film, and a second electrode film on a substrate; forming a groove that separates the second electrode film, the second insulating film and the first electrode film; forming an insulating film inside the groove so that an upper surface thereof is positioned between upper surfaces of the second electrode film and the second insulating film; forming an overhung portion on the second electrode film so as to overhang on the insulating film by performing a selective growth process; and forming a low resistance layer at the overhung portion and the second electrode film by performing an alloying process.

Abstract: A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film between the floating and the control gate electrode; a pair of select gate transistors on the semiconductor substrate with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode; a polyplug of the first thickness situated between the second gate electrodes of the pair of select gate transistors; and a metal plug provided on the polyplug.

Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor region surrounded with an element isolation region, a first insulating film formed on the semiconductor region, a pair of resistance elements located at the semiconductor region, each resistance element including a first conductive film formed on the first insulating film, a second insulating film formed on the first conductive film and a second conductive film formed on the second insulating film, a pair of first contact plugs formed on one of the resistance elements and arranged along a first direction relative to the semiconductor region, and a pair of second contact plugs formed on the other resistance element and arranged along the first direction. A first width of the resistance element is a second direction which is perpendicular to the first direction is smaller than half of a second width of the semiconductor region in the second direction.

Abstract: According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device including: sequentially forming a first insulating film, a first electrode film, a second insulating film, and a second electrode film on a substrate; forming a groove that separates the second electrode film, the second insulating film and the first electrode film; forming an insulating film inside the groove so that an upper surface thereof is positioned between upper surfaces of the second electrode film and the second insulating film; forming an overhung portion on the second electrode film so as to overhang on the insulating film by performing a selective growth process; and forming a low resistance layer at the overhung portion and the second electrode film by performing an alloying process.

Abstract: A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film between the floating and the control gate electrode; a pair of select gate transistors on the semiconductor substrate with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode; a polyplug of the first thickness situated between the second gate electrodes of the pair of select gate transistors; and a metal plug provided on the polyplug.

Abstract: A nonvolatile semiconductor memory includes a memory cell array, a page buffer that is connected to the memory cell array and retains program verification results of a write-in operation of repeating data write-in and program verification, a bit scan circuit that is connected to the page buffer and determines whether or not the number of fail bits is equal to or less than number of reference bits based on the program verification results retained in the page buffer, a register that is connected to the bit scan circuit and retains determination results of the bit scan circuit, and a sequencer that controls the write-in operation and an operating sequence of the bit scan circuit and terminates the write-in operation while leaving the number of fail bits in response to the results temporarily stored in the register.

Abstract: A nonvolatile semiconductor memory includes a memory ell array, a page buffer that is connected to the memory cell array and retains program verification results of a write-in operation of repeating data write-in and program verification, a bit scan circuit that is connected to the page buffer and determines whether or not the number of fail bits is equal to or less than number of reference bits based on the program verification results retained in the page buffer, a register that is connected to the bit scan circuit and retains determination results of the bit scan circuit, and a sequencer that controls the write-in operation and an operating sequence of the bit scan circuit and terminates the write-in operation while leaving the number of fail bits in response to the results temporarily stored in the register.