Patents by Inventor Yugo Takeda

Yugo Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11774991
    Abstract: An information processing apparatus capable of controlling vibration in accordance with a situation in a case where the vibration is generated on the basis of an audio signal. The information processing apparatus can include: a vibrator; and a controller configured to detect a state of the information processing apparatus and control a state of the vibrator based on a detection result, in which the controller controls vibration the vibrator in accordance with reproduction of content while the content is being reproduced in the information processing apparatus, and, in a case where a predetermined condition is satisfied, restricts vibration of the vibrator even while the content is being reproduced in the information processing apparatus.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 3, 2023
    Assignee: SONY CORPORATION
    Inventors: Shuhei Miyazaki, Yugo Takeda, Takeshi Matsui, Taku Tomita, Seiji Muramatsu, Ryoko Amano, Risa Takahashi, Ikuo Yamano, Takeshi Ogita, Ayumi Kato, Ryo Yokoyama
  • Patent number: 11302719
    Abstract: A thin film transistor substrate includes: a plurality of gate signal lines extending in a first direction; a plurality of gate lead-out lines and a plurality of dummy gate lead-out lines extending in a second direction; a plurality of common lines extending in at least one of the first direction and the second direction in the pixel region; and a common electrode provided opposite to a pixel electrode and electrically connected to the plurality of common lines. The plurality of gate lead-out lines are connected to the gate signal lines at least at one point of a plurality of intersections between the plurality of gate signal lines and the plurality of gate lead-out lines, and the common potential is applied to the plurality of dummy gate lead-out lines.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 12, 2022
    Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventors: Yugo Takeda, Masafumi Hirata, Hiroaki Iwato
  • Publication number: 20200401164
    Abstract: To provide an information processing apparatus capable of controlling vibration in accordance with a situation in a case where the vibration is generated on the basis of an audio signal. Provided is an information processing apparatus including: a vibration unit; and a control unit configured to detect a state of the own apparatus and control a state of the vibration unit on the basis of a detection result, in which the control unit vibrates the vibration unit in accordance with reproduction of content while the content is being reproduced in the own apparatus, and, in a case where a predetermined condition is satisfied, restricts vibration of the vibration unit even while the content is being reproduced in the own apparatus.
    Type: Application
    Filed: December 26, 2018
    Publication date: December 24, 2020
    Applicant: Sony Corporation
    Inventors: Shuhei MIYAZAKI, Yugo TAKEDA, Takeshi MATSUI, Taku TOMITA, Seiji MURAMATSU, Ryoko AMANO, Risa TAKAHASHI, Ikuo YAMANO, Takeshi OGITA, Ayumi KATO, Ryo YOKOYAMA
  • Publication number: 20200176481
    Abstract: A thin film transistor substrate includes: a plurality of gate signal lines extending in a first direction; a plurality of gate lead-out lines and a plurality of dummy gate lead-out lines extending in a second direction; a plurality of common lines extending in at least one of the first direction and the second direction in the pixel region; and a common electrode provided opposite to a pixel electrode and electrically connected to the plurality of common lines. The plurality of gate lead-out lines are connected to the gate signal lines at least at one point of a plurality of intersections between the plurality of gate signal lines and the plurality of gate lead-out lines, and the common potential is applied to the plurality of dummy gate lead-out lines.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 4, 2020
    Inventors: Yugo TAKEDA, Masafumi HIRATA, Hiroaki IWATO
  • Patent number: 9287296
    Abstract: Provided is a display device, in which: a plurality of spacers placed between a first substrate and a second substrate include a first spacer placed between a first thin film transistor and a second thin film transistor and a second spacer placed between the first thin film transistor and a third thin film transistor; and a distance between a center of the first spacer and a center of a line width of a first data line is smaller than a distance between a center of the second spacer and a center of a line width of a second data line.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 15, 2016
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Yuuta Funahashi, Masafumi Hirata, Yugo Takeda
  • Publication number: 20150060858
    Abstract: Provided is a display device, in which: a plurality of spacers placed between a first substrate and a second substrate include a first spacer placed between a first thin film transistor and a second thin film transistor and a second spacer placed between the first thin film transistor and a third thin film transistor; and a distance between a center of the first spacer and a center of a line width of a first data line is smaller than a distance between a center of the second spacer and a center of a line width of a second data line.
    Type: Application
    Filed: March 6, 2014
    Publication date: March 5, 2015
    Applicant: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Yuuta FUNAHASHI, Masafumi HIRATA, Yugo TAKEDA
  • Publication number: 20130045368
    Abstract: A PDP includes a front plate, a rear plate, and a sealing layer. The rear plate includes a display region between the rear plate and the front plate, and a non-display region around the display region. The rear plate includes a terminal area located in the non-display region, and a base dielectric layer. The sealing layer is laid in the non-display region, and has plural bead members. The base dielectric layer covers the display region and a portion of the terminal area without sticking outward from the sealing layer. The sealing layer is partially located between a region of the base dielectric layer that covers the terminal area, and the front plate. An edge of a region of the base dielectric layer that covers the terminal area is covered with the sealing layer, and is present at substantially the same position where an edge of the front plate is present.
    Type: Application
    Filed: April 20, 2012
    Publication date: February 21, 2013
    Inventors: Yugo Takeda, Hideki Oku, Hiroyuki Isse
  • Patent number: 8262429
    Abstract: A method for producing a plasma display panel includes the steps of: evacuating air from a discharge space formed between a front plate and a rear plate which are substrates facing each other through piping; introducing a discharge gas into the discharge space through gas piping that branches from the piping; and recovering the discharge gas remaining in the piping system through the piping.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 11, 2012
    Assignee: Panasonic Corporation
    Inventors: Masafumi Okawa, Yoshiki Sasaki, Takeo Funaoka, Toshiyuki Watanabe, Masaki Nishinaka, Mamoru Watanabe, Jun-ichi Taira, Yugo Takeda
  • Publication number: 20110250817
    Abstract: A method for producing a plasma display panel includes the steps of: evacuating air from a discharge space formed between a front plate and a rear plate which are substrates facing each other through piping; introducing a discharge gas into the discharge space through gas piping that branches from the piping; and recovering the discharge gas remaining in the piping system through the piping.
    Type: Application
    Filed: November 16, 2010
    Publication date: October 13, 2011
    Inventors: Masafumi Okawa, Yoshiki Sasaki, Takeo Funaoka, Toshiyuki Watanabe, Masaki Nishinaka, Mamoru Watanabe, Jun-ichi Taira, Yugo Takeda