Abstract: A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturing steps. The method for manufacturing a semiconductor device includes the steps of: forming a first ion implantation expendable film and an etching mask film on a first conductive type semiconductor substrate; patterning the etching mask film into a shape of an active and field region; introducing dopant into the substrate; forming a trench groove on the substrate; forming an insulation film in the trench groove; forming a first well; flattening the insulation film; removing the etching mask film; removing the expendable film; forming a second ion implantation expendable film on the substrate; forming a mask pattern; and forming a second well by introducing dopant into the substrate.

Abstract: A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturing steps. The method for manufacturing a semiconductor device includes the steps of: forming a first ion implantation expendable film and an etching mask film on a first conductive type semiconductor substrate; patterning the etching mask film into a shape of an active and field region; introducing dopant into the substrate; forming a trench groove on the substrate; forming an insulation film in the trench groove; forming a first well; flattening the insulation film; removing the etching mask film; removing the expendable film; forming a second ion implantation expendable film on the substrate; forming a mask pattern; and forming a second well by introducing dopant into the substrate.

Abstract: The present invention has the object of offering a semiconductor production method which simplifies the fabrication of gate electrodes for MOS-type semiconductor elements and allows a high yield to be maintained. For this purpose, it has steps of forming a field-shield gate insulation film on a semiconductor substrate, forming polycrystalline silicon films having an etching rate which is greater at an upper side than a lower side thereon, and etching the polycrystalline silicon films under conditions which allow for side etching with the silicon oxide film as a mask, so as to make gradually tapered inclines on side walls of field-shield gate electrode.

Abstract: A nonvolatile semiconductor memory device including a plurality of memory cells, and a method of making this memory device.

Abstract: A nonvolatile semiconductor storage device in which a composite gate of a floating gate memory cell transistor and a gate electrode of a peripheral MOS transistor are formed in the same lithography process and a manufacturing method thereof. A polycrystalline silicon film and an ONO film are formed on a well region through a gate oxide film and a tunnel oxide film. A polycrystalline silicon film is formed after removing the ONO film in the right region. A floating gate and a control gate of the memory cell transistor and a gate electrode of the select transistor are formed with photoresist as a mask. Thereafter, ions of impurities are implanted and diffused in a transverse direction, thereby to form an impurity diffused layer. With this, since the impurity diffused layer is formed by transverse diffusion of impurities after the tunnel oxide film is formed, it is possible to prevent deterioration of the film quality of the tunnel oxide film.

Abstract: A mask ROM with increased memory capacity is disclosed. Besides MOS transistors each comprising a memory cell, MOS field shield transistors for device isolation, originally provided for electrically isolating the memory cell transistors, are also used as additional memory cells in addition to providing their isolating function. To write data in one of the field shield transistor, the threshold voltage of the field shield transistor is lowered, compared to field shield transistors in other regions. This is done by ion implantation of an n-type impurity into a p-type silicon substrate in a region beneath a gate electrode of the field shield transistor (a channel region). Data is read by judging on/off of the transistors when an intermediate voltage, between a high threshold voltage and a low threshold voltage is applied to a field shield line.

Abstract: A non-volatile semiconductor memory unit comprises a memory cell having a semiconductor substrate, a control gate formed over the semiconductor substrate, an electric charge accumulative layer formed between the semiconductor substrate and the control gate, and a source and drain, both formed in the semiconductor substrate. The memory cell stores N-valued data (N being an integer more than 3) by accumulating an electric charge in the electric charge accumulative layer. A detector is provided for detecting a storage state before data rewrite of the memory cell. A comparison circuit compares the storage state before data rewrite, with a storage state after data rewrite to produce a difference therebetween. A rewrite circuit is included for rewriting the storage state of the memory cell by applying N-1 levels of predetermined voltages to the source, the drain and control gate of the memory cell, respectively, in accordance with the produced difference.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of spaced field-shield isolation structures formed on a surface of the substrate and extending parallelly in a first direction to provide element-forming regions at spaces between every adjacent two of the field-shield element isolation layers, a pair of impurity diffusion layers of a second conductivity type different from the first conductivity type formed in the surface of the substrate at portions adjacent opposite sides of each of the element-forming regions, a plurality of spaced lateral regions defined on the surface of the substrate and extending parallelly in a second direction intersecting with the first direction; and a plurality of discrete gate electrodes formed on the surface of the substrate at portions corresponding to intersections of the lateral and element-forming regions, respectively, in electrically insulated relationship with the substrate, the gate electrodes being aligned along the late

Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate, a shield gate electrode formed over a device isolation region of the semiconductor substrate through a shield gate insulating film, a floating gate electrode formed over a device region of the semiconductor substrate through a tunnel insulating film, the device region lying adjacent to the device isolation region and a part of the floating gate electrode overlapping the device isolation region so as to form a gap region therebetween, and a control gate electrode formed over the floating gate electrode through an oxide/nitride/oxide (ONO) film and formed over the shield gate electrode through a shield cap insulating film such that a part of the control gate electrode extends into the gap region.

Abstract: An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

Abstract: A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a plurality of reference cells disposed on each of the row lines. Each memory cell includes an MOS transistor having a substrate, a spaced-apart drain and source formed on one surface of the substrate, a channel region between the drain and source and a lamination of a tunnel insulating film, a floating gate, an interlayer insulating film and a control gate formed in that order on the channel region.

Abstract: A part of a polycrystalline silicon film forming a grounding line in a memory cell of a high-resistance load type SRAM, located immediately below a contact hole for connection between a polysilicon power supply line part and an aluminum power supply line part, is separated and isolated from the remaining part of the polycrystalline silicon film to form an island-like part. The contact hole extends through an interlayer insulating film below the aluminum power supply line part, the polysilicon power supply line part and another interlayer insulating film above the island part, and reaches the island part, whereby the aluminum power supply line part contacts even the island part through the contact hole. The island part also contacts the polysilicon power supply line part through another contact hole, whereby low-resistance contact can be obtained between the aluminum and polysilicon power supply line parts through the island part.

Abstract: A semiconductor memory having a memory cell including a stacked capacitor in which a lower electrode contacting one of two diffusion regions of an access transistor is formed in the form of two layers. It is preferable that impurities having a smaller diffusion coefficient, or arsenic is introduced into a first layer of the lower electrode contacting the diffusion region, and impurities having a larger diffusion coefficient, or phosphorus is introduced into a second layer of the lower electrode contacting capacitor dielectric film. Since a diffusion coefficient of arsenic is small, it is possible to prevent the junction of the diffusion region from becoming deep and on the other hand since phosphorus is introduced into the second polycrystalline Si film contacting the capacitor dielectric film, it is possible to prevent the degradation of the film quality of the capacitor dielectric film.