Abstract: An electronic apparatus and a booting method are provided. The electronic apparatus comprises a processing unit, a firmware unit and a memory. In the booting method, a boot code is read from the firmware unit by the processing unit for executing a booting initialization procedure. Whether a new version firmware code exists in a first block of the memory is determined by the boot code. If the new version firmware code exists in the first block, the new version firmware code is loaded into a second block of the memory by the boot code, and the new version firmware code is read from the second block so as to execute a booting procedure for loading an operating system.

Abstract: A method for remotely powering on a host, a system using the method, and an electronic apparatus using the method are provided. In the method, a control apparatus is employed to connect a server and detect whether the server receives a booting command from a remote apparatus. When it is detected that the server receives the booting command, an activation signal is transmitted to the host by the control apparatus, so as to power on the host.

Abstract: A computer apparatus and a method for charging a portable electronic device are provided. The method is implemented in a computer apparatus including a connector. The method includes: (a) detecting whether the portable electronic device is plugged and connected to the connector when the computer apparatus is in a power off state; (b) causing the computer apparatus to execute a boot process if the portable electronic device is plugged and connected to the connector; (c) determining whether the portable electronic device is a predetermined device; (d) sending a charging command to the portable electronic device such that the portable electronic device derives a charging current from the computer apparatus if the portable electronic device is the predetermined device; and (e) causing the computer apparatus to shut down before an operating system is loaded.

Abstract: A method for detecting hardware suitable for an electronic apparatus is provided. In the method, a booting signal is received. A graphical interface is started. The graphical interface includes a mainboard layout. And each connector is detected for obtaining peripheral hardware configured in the electronic apparatus. A figure corresponding to the peripheral hardware configured in the electronic apparatus and a location information of the peripheral hardware on a mainboard are obtained from a database. The figure is placed on a corresponding connector location of the mainboard layout.

Abstract: An electronic apparatus and a booting method are provided. The electronic apparatus comprises a processing unit, a firmware unit and a memory. In the booting method, a boot code is read from the firmware unit by the processing unit for executing a booting initialization procedure. Whether a new version firmware code exists in a first block of the memory is determined by the boot code. If the new version firmware code exists in the first block, the new version firmware code is loaded into a second block of the memory by the boot code, and the new version firmware code is read from the second block so as to execute a booting procedure for loading an operating system.

Abstract: A computer apparatus and a method for charging a portable electronic device are provided. The method is implemented in a computer apparatus including a connector. The method includes: (a) detecting whether the portable electronic device is plugged and connected to the connected when the computer apparatus is in a power off state; (b) causing the computer apparatus to execute a boot process if the portable electronic device is plugged and connected to the connector; (c) determining whether the portable electronic device is a predetermined device; (d) sending a charging command to the portable electronic device such that the portable electronic device derives a charging current from the computer apparatus if the portable electronic device is the predetermined device; and (e) causing the computer apparatus to shut down before an operating system is loaded.

Abstract: The invention provides a method for reducing booting time and a computer using the same. The method includes the following steps. The computer is shut down. After the step of shutting down the computer, the computer is booted up to make the computer enter into a power-saving mode. Thus, when a user performs an operation to boot up the computer, the computer resumes a normal state from the power-saving mode.

Abstract: A computer system comprises a chip set having a PCI Express controller with a preset lane width, a PCI Express connector with a relative bigger lane width, and a PCI Express interfaced apparatus with the bigger lane width. In the system, only part of the contacts within the PCI Express connector is connected to the PCI Express controller while the other contacts are opened.

Abstract: A computer system comprising a chipset, a PCI Express connector with a preset bandwidth, and a PCI Express daughter board with a bigger bandwidth, is provided. The chipset is provided with a PCI Express controller with the preset bandwidth and electrically connects to the PCI Express connector. The PCI Express connector has a trench formed at an edge thereof. The PCI Express daughter board has a connecting portion with a number of golden fingers greater than a number of contacts of the PCI connector. The PCI Express connector is capable to pair the daughter board with part of the golden fingers located outside the connector.

Abstract: A computer system comprising a chipset, a PCI Express connector with a preset bandwidth, and a PCI Express daughter board with a bigger bandwidth, is provided. The chipset is provided with a PCI Express controller with the preset bandwidth and electrically connects to the PCI Express connector. The PCI Express connector has a trench formed at an edge thereof. The PCI Express daughter board has a connecting portion with a number of golden fingers greater than a number of contacts of the PCI connector. The PCI Express connector is capable to pair the daughter board with part of the golden fingers located outside the connector.

Abstract: A computer system comprises a chip set having a PCI Express controller with a preset lane width, a PCI Express connector with a relative bigger lane width, and a PCI Express interfaced apparatus with the bigger lane width. In the system, only part of the contacts within the PCI Express connector is connected to the PCI Express controller while the other contacts are opened.

Abstract: A connector that may indicate an edition of a connecting interface of a computer, includes a host controller, and an indicator electrically connected to the host controller. The host controller includes a judging device used to judge a transmitting velocity between the host of the computer and the peripheral device. Thus, the indicator may be adapted to indicate the edition of the connecting interface according to the transmitting velocity between the host of the computer and the peripheral device.

Abstract: A device for selectively providing read-only data includes an inter-integrated circuit (I2C) controller, an AND-gate, a decoder, and m ROMs that each have different data that can be accessed by the I2C controller. M pads which connected to the AND-gate and the decoder are used as enable-signal input terminals. A specific pin in the chip is connected to one of the pads to receive the enable-signal and other pads for the enable-signal input terminals are connected during the packaging process so that they have constant voltage as the device is operating. When the status of the enable-signal changes, the decoder selects the ROM that corresponds to the specific pad and enables the I2C controller to access the data in the ROM.

Abstract: A connector that may indicate an edition of a connecting interface of a computer, includes a host controller, and an indicator electrically connected to the host controller. The host controller includes a judging device used to judge a transmitting velocity between the host of the computer and the peripheral device. Thus, the indicator may be adapted to indicate the edition of the connecting interface according to the transmitting velocity between the host of the computer and the peripheral device.

Abstract: A dual solder-hole layout for expansion slots is disclosed. The dual solder-hole layout, which comprises a first solder-hole layout and a second solder-hole layout, can be electrically connected to one of various types of expansion slots. The first solder-hole layout comprises a first solder-hole row and a second solder-hole row. Solder holes in the first solder-hole row form a straight line. The second solder-hole row is separated into a first solder-hole portion and a second solder-hole portion. The first solder-hole portion of the second solder-hole row is parallel to the first solder-hole row but far from the first solder-hole row. The second solder-hole portion of the second solder-hole row is also parallel to the first solder-hole row and is closer to the first solder-hole row. The second solder-hole layout comprises a third solder-hole row. The third solder-hole row is parallel to the first solder-hole row and the first solder-hole portion of the second solder-hole row.

Abstract: A software write protection method for protecting the values in the registers of a programmable chip of a computer system. After setting the registers of the programmable chip, the computer system works according to the set function. Any tampering with data inside the register of the programmable chip is not allowed. When virus programs attempt to write erroneous data into the programmable chip, virus commands are changed by the interrupt service program. Hence, unnecessary changes to the values within the register of the programmable chip are prevented leading to a greater stability for the computer system.

Abstract: A method and an installation for preventing premature termination of BIOS refresh operation due to accidental pressing of the reset button. A chipset issues a restrain signal to a logic device when the BIOS is carrying out data refresh so as to restrain any reset command issued from a reset device. At the end of the refresh operation, the chipset issues a non-restrain signal to the logic device granting any request for system reset when the reset device is pressed. With such arrangement, trouble with re-starting a computer after the interruption of a BIOS refresh operation by an unwanted system reset can be avoided.

Abstract: A computer system comprising a chipset, a PCI Express connector with a preset bandwidth, and a PCI Express daughter board with a bigger bandwidth, is provided. The chipset is provided with a PCI Express controller with the preset bandwidth and electrically connects to the PCI Express connector. The PCI Express connector has a trench formed at an edge thereof. The PCI Express daughter board has a connecting portion with a number of golden fingers greater than a number of contacts of the PCI connector. The PCI Express connector is capable to pair the daughter board with part of the golden fingers located outside the connector.